SCAN CLOCK GATING CONTROLLER AND METHOD FOR PERFORMING STUCK-AT FAULT TEST AMONG MULTIPLE BLOCK CIRCUITS

    公开(公告)号:US20240353489A1

    公开(公告)日:2024-10-24

    申请号:US18635036

    申请日:2024-04-15

    IPC分类号: G01R31/3185 G01R31/317

    摘要: A scan clock gating controller and a method for performing a stuck-at fault test among multiple block circuits are provided. The scan clock gating controller includes a decoder and multiple clock gating circuits. The decoder is configured to generate multiple one-hot control signals according to a selection signal. The multiple clock gating circuits are configured to generate multiple final scan clocks to the multiple block circuits according to the multiple one-hot control signals, a scan enable signal and an initial scan clock. When the scan enable signal has a first logic value, the multiple clock gating circuits enable the multiple final scan clocks, respectively. When the scan enable signal has a second logic value, the multiple clock gating circuits control whether to enable the multiple final scan clocks according to the multiple one-hot control signals, respectively.

    ELECTRONIC DEVICE FOR PERFORMING COMMUNICATIONS WITH MASTER DEVICE BY SERIAL COMMUNICATIONS BUS AND METHOD FOR PERFORMING ASSIGNMENT OF IDENTIFIER ON ELECTRONIC DEVICE

    公开(公告)号:US20240345974A1

    公开(公告)日:2024-10-17

    申请号:US18624092

    申请日:2024-04-01

    IPC分类号: G06F13/362 G06F13/42

    CPC分类号: G06F13/3625 G06F13/4291

    摘要: An electronic device for performing communication with a master device via a serial communications bus and a method for performing assignment of an identifier on the electronic device are provided, wherein the master device is coupled to multiple slave devices via the serial communications bus, and the multiple slave devices include the electronic device. The electronic device includes a clock terminal, a data terminal, and a determination circuit coupled to the clock terminal and the data terminal, wherein the clock terminal and the data terminal receive a first signal and a second signal from the master device, respectively. The determination circuit determines whether a time point of pulling down the first signal is earlier than a time point of pulling down the second signal, in order to generate a determination result, wherein the assignment of the identifier of the electronic device is controlled according to the determination result.

    Multi-link device adopting block acknowledgment and packet allocation method thereof

    公开(公告)号:US12120036B2

    公开(公告)日:2024-10-15

    申请号:US17903059

    申请日:2022-09-06

    摘要: A multi-link device includes a first link queue, a second link queue, a control circuit, a first transmitter and a second transmitter. The control circuit includes a common queue for buffering a plurality of packets, each packet having a sequence number. The control circuit obtains a minimum sequence number of all packets in the first link queue and the second link queue, computes a maximum sequence number according to the minimum sequence number and a block acknowledgment window size, determines whether to allocate a set of packets from the common queue according to the maximum sequence number, and if so, allocates the set of packets to the first link queue and/or the second link queue. The first transmitter transmits a packet from the first link queue to a first receiving device, and the second transmitter transmits a packet from the second link queue to a second receiving device.

    Semiconductor device and method for generating test pulse signals

    公开(公告)号:US12105144B2

    公开(公告)日:2024-10-01

    申请号:US17730243

    申请日:2022-04-27

    IPC分类号: G01R31/317 G06F1/10

    CPC分类号: G01R31/31726 G06F1/10

    摘要: A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

    MULTI-LINK DEVICE OF DISPATCHING PACKETS ACCORDING TO TRANSMISSION CONDITION AND LINK USAGE INFORMATION AND METHOD OF CONTROLLING THE SAME

    公开(公告)号:US20240323999A1

    公开(公告)日:2024-09-26

    申请号:US18525875

    申请日:2023-12-01

    发明人: Cheng-Hsuan Wu

    IPC分类号: H04W72/56 H04W72/12

    CPC分类号: H04W72/56 H04W72/12

    摘要: A multi-link transmission device includes a first transmission module, a second transmission module, an analysis module and a multi-link control module. The first transmission module transmits each packet in the first transmission module via a first link, and transmits a first transmission condition for each pack transmission for the first transmission module. The second transmission module transmits each packet in the second transmission module via a second link, and transmits a second transmission condition for each pack transmission for the second transmission module. The analysis module computes a ratio of packet consumption rates of the first transmission module and the second transmission module according to the first transmission condition and the second transmission condition. The multi-link control module dispatches a packet to the first transmission module or the second transmission module according to at least the ratio of the packet consumption rates.

    PACKET IDENTIFICATION SYSTEM AND PACKET IDENTIFICATION METHOD

    公开(公告)号:US20240314068A1

    公开(公告)日:2024-09-19

    申请号:US18512144

    申请日:2023-11-17

    发明人: CHUNG-CHANG LIN

    IPC分类号: H04L45/00 H04L45/42

    CPC分类号: H04L45/566 H04L45/42

    摘要: A packet identification system and a packet identification method are provided. The packet identification system receives a target packet, and includes a first packet header analyzer, a host, and a second packet header analyzer. The first packet header analyzer is configured to preset a plurality of first packet header formats, and identifies whether or not the target packet is one of a plurality of first packet types according to the first packet header formats. The host is configured to dynamically set at least one second packet header format. The second packet header analyzer is communicatively connected to the host. The second packet header analyzer is configured to store the at least one second packet header format, and identifies whether or not the target packet is at least one second packet type according to the at least one second packet header format.

    WIRELESS COMMUNICATION DEVICE AND ASSOCIATED INTERFERENCE DETECTION METHOD

    公开(公告)号:US20240313872A1

    公开(公告)日:2024-09-19

    申请号:US18592486

    申请日:2024-02-29

    IPC分类号: H04B17/345 H04B7/06

    CPC分类号: H04B17/345 H04B7/0626

    摘要: A wireless communication device includes a wireless transceiver circuit, a baseband signal processing circuit, and an interference detection device. The wireless transceiver circuit receives a wireless signal from a wireless transmission channel, and converts the wireless signal into a baseband signal. The baseband signal processing circuit processes the baseband signal including a plurality of packets. The interference detection device is coupled to the baseband signal processing circuit, and performs a short-term interference detection and a long-term interference detection according to the plurality of packets, to determine whether interference exists in the wireless transmission channel and generate a detection result, wherein the short-term interference detection is an interference detection within a single packet, and the long-term interference detection is an interference detection across packets. When the detection result indicates interference exists in the wireless transmission channel, the detection result further indicates a frequency band in which the interference exists.

    Audio system with dynamic target listening spot and ambient object interference cancelation

    公开(公告)号:US12096203B2

    公开(公告)日:2024-09-17

    申请号:US17993461

    申请日:2022-11-23

    发明人: Kai-Hsiang Chou

    摘要: An audio system is proposed, dynamically playing optimized audio signals based on user position. A sensor circuits dynamically senses a target space to generate field context information. First speaker and second speaker are arranged for audio playback. A host device recognizes a user from the field context information, determines the user position corresponding to the target space, and adaptively assigns the user position as a target listening spot. A sensor circuit contains a camera capturing an ambient image out of the target space. A control circuit utilizes a user interface circuit to perform a configuration procedure which determines location, size and acoustic attribute information of an ambient object, allowing the control circuit to accordingly perform an object-based compensation operation on the target listening spot to generate optimized first channel audio signal and second channel audio signal.