公开(公告)号：USRE35254E

公开(公告)日：1996-05-28

申请号：US238822

申请日：1994-05-05

Applicant: Philippe Chaisemartin ,  Sylvain Kritter

Inventor： Philippe Chaisemartin ,  Sylvain Kritter

IPC: H03J3/04 ,  G06F5/06 ,  H03K5/00 ,  H03M7/00 ,  H03M7/14 ,  H04L7/00 ,  H04L25/05 ,  H04J1/05 ,  H03B19/00

CPC classification number: H04L25/05 ,  G06F5/06

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.

Abstract translation: 用于将包括以频率F致动的一系列第一单位寄存器（R4-R0）的串行位的流量加倍或除以2的装置; 以频率2F致动的第二寄存器（R）; 连接到第一寄存器的第一（R4）的输入端的输入端（IN），并通过第一门（T5）连接到连接到第二寄存器的输入端的内部线（L） 连接到每个第二（R3）的输入的第一多路复用器（M4-M1）到第一寄存器的最后（R0），用于选择前一个寄存器的输出或内部线，或者仍然是第二寄存器的输出; 第二多路复用器（M），其选择第一寄存器的最后（R0）的输出或第二寄存器的输出或填充位; 每个第一寄存器的输出和内部线路之间的第二传输门（T4-T0）; 以及用于控制各种门和多路复用器的装置。

公开(公告)号：US5159207A

公开(公告)日：1992-10-27

申请号：US618281

申请日：1990-11-28

Applicant: Antoine Pavlin ,  Thierry Sicard ,  Marc Simon

Inventor： Antoine Pavlin ,  Thierry Sicard ,  Marc Simon

IPC: H01L21/761 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H03K17/081

CPC classification number: H03K17/08104 ,  H01L27/0218 ,  H01L27/0251 ,  Y10T307/839

Abstract: A dynamic isolation circuit belonging to a monolithic integrated circuit comprising lateral transistors and vertical transistors. The lateral transistors are isolated by an isolating region connected to an isolating potential (V.sub.iso), these lateral transistors being connected up to voltages of a first polarity relative to a reference voltage (GND), the power terminal connected up to the rear face normally being at a potential (V.sub.out) of the first polarity relative to the reference voltage. This circuit comprises a sign-detector (D) for detecting the sign of the potential of the rear face relative to the reference voltage, at least one lateral transistor (S1) to connect the isolating potential to the reference potential when the potential of the rear face is of the first polarity relative to the reference potential, and at least one vertical transistor (S2) to connect the isolating potential to the potential of the rear face when the potential of the rear face is of the second polarity relative to the reference potential.

Abstract translation: 属于单片集成电路的动态隔离电路，其包括横向晶体管和垂直晶体管。 横向晶体管通过连接到隔离电位（Viso）的隔离区隔离，这些横向晶体管相对于参考电压（GND）连接到第一极性的电压，通常连接到后面的电源端子 处于相对于参考电压的第一极性的电位（Vout）。 该电路包括用于检测背面相对于参考电压的电位的符号的符号检测器（D），至少一个横向晶体管（S1），以在后方的电位将绝缘电位连接到参考电位 面相对于参考电位具有第一极性，以及至少一个垂直晶体管（S2），用于当背面的电位相对于参考电位具有第二极性时，将隔离电位连接到后表面的电位 。

公开(公告)号：US5134322A

公开(公告)日：1992-07-28

申请号：US637918

申请日：1991-01-07

Applicant: Jean-Marie Bourgeois ,  Marco Bildgen

Inventor： Jean-Marie Bourgeois ,  Marco Bildgen

IPC: H03K17/06

CPC classification number: H03K17/063

Abstract: A control and monitoring circuit for a power switch comprises a first portion (20) connected to this switch and fed with reference to a floating voltage (V.sub.F) of an electrode of this switch, a second portion (10) connected to circuits external to the switch and fed with reference to a fixed voltage, a coder (40) arranged on the side of the second portion and a suitable decoder (50) arranged on the side of the first portion.

Abstract translation: 用于电源开关的控制和监视电路包括连接到该开关并参考该开关的电极的浮动电压（VF）馈送的第一部分（20），连接到该开关外部的电路的第二部分（10） 参考固定电压进行切换和馈送，布置在第二部分侧面的编码器（40）和布置在第一部分侧面上的合适的解码器（50）。

公开(公告)号：US5943264A

公开(公告)日：1999-08-24

申请号：US067494

申请日：1998-04-27

Applicant: Richard Fournel ,  Fabrice Marinet

Inventor： Richard Fournel ,  Fabrice Marinet

IPC: G11C17/16 ,  G11C16/04

CPC classification number: G11C17/16

Abstract: A memory cell in an integrated circuit using CMOS technology includes the following in series: an N type selection MOS transistor and a PN semiconductor junction. The source of the transistor is connected to the N type zone of the junction by a metal contact made on at least a part of the N type zone. The method of control includes, in the programming mode, the application to the integrated circuit of a level of supply voltage greater than a nominal value, within an upper limit that is permissible for the integrated circuit, and the application of this level to the drain and the gate of the selection transistor. The selection transistor is made with a channel having a length smaller than or equal to the minimum length in the technology considered. Accordingly, the selection transistor is biased in the snap-back mode. The memory cell may be used in a memory circuit in matrix form.

Abstract translation: 使用CMOS技术的集成电路中的存储单元包括以下串联：N型选择MOS晶体管和PN半导体结。 晶体管的源极通过在N型区域的至少一部分上形成的金属接触而连接到接合部的N型区域。 控制方法包括在编程模式下，在集成电路允许的上限范围内将集成电路的电源电压大于标称值的应用，以及将该电平应用于漏极 和选择晶体管的栅极。 选择晶体管由所考虑的技术中具有长度小于或等于最小长度的沟道制成。 因此，选择晶体管在快速恢复模式下被偏置。 存储单元可以以矩阵形式用于存储器电路。