公开(公告)号：US10733666B1

公开(公告)日：2020-08-04

申请号：US11173725

申请日：2005-06-30

Applicant: Michael J. Wookey ,  Michael J. Gionfriddo

Inventor： Michael J. Wookey ,  Michael J. Gionfriddo

IPC: G06Q40/00

Abstract: Methods, systems, and articles of manufacture are provided for defining a privacy zone between an asset platform and an offering platform within a network. A request is received from a customer for an offering to be deployed in association with an asset hosted on the asset platform. The offering has back-end offering logic and front-end offering logic that is operatively configured to collect and transfer a data element associated with the asset to the back-end offering logic. A privacy policy associated with the offering is identified. The front-end offering logic is deployed to the asset platform such that the front-end offering logic is operatively configured to communicate with the asset. A data element collection filter is then generated between the front-end offering logic and the back-end offering logic to control the transfer and the access of the data element in accordance with the privacy policy.

公开(公告)号：US08543843B1

公开(公告)日：2013-09-24

申请号：US11933349

申请日：2007-10-31

Applicant: Yu Qing Cheng ,  John Gregory Favor ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

Inventor： Yu Qing Cheng ,  John Gregory Favor ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46

CPC classification number: G06F9/3851

Abstract: A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.

Abstract translation: 包括一个或多个物理核心的虚拟核心管理系统，包括与执行程序相关联的逻辑状态集合的虚拟核心以及被配置为将所述虚拟核心映射到所述一个或多个物理内核之一的虚拟核心管理组件 基于电源管理的考虑。

公开(公告)号：US20110141868A1

公开(公告)日：2011-06-16

申请号：US12639200

申请日：2009-12-16

Applicant: Faramarz Mahnad

Inventor： Faramarz Mahnad

IPC: G11B27/36

CPC classification number: G11B20/1202 ,  G11B7/003 ,  G11B7/00458 ,  G11B7/14 ,  G11B7/24009 ,  G11B27/107 ,  G11B27/24 ,  G11B27/322 ,  G11B27/36 ,  G11B2020/1238 ,  G11B2020/1267 ,  G11B2220/93

Abstract: Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage. Methods and systems of tape technology disclose optical tape media including: configurations, formulations, markings, and structure; optical tape manufacturing methods, systems, and apparatus methods and systems including: curing processes, coating methods, embossing, drums, testing, tracking alignment stamper strip; optical tape methods and systems including: pick up head adapted for the disclosed optical tape; and optical tape uses including optical storage media devices for multimedia applications

公开(公告)号：US20110138372A1

公开(公告)日：2011-06-09

申请号：US12631256

申请日：2009-12-04

Applicant: Peter Carl Damron

Inventor： Peter Carl Damron

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.

Abstract translation: 本公开提供了一种在注册分配之前减少或消除过多的注册压力或虚拟寄存器超过目标计算设备的物理寄存器的程序的代码中的位置的编译器预扩展阶段。 预戳阶段标识过多寄存器压力的点，选择候选虚拟寄存器，选择虚拟寄存器从候选者预先插入，并插入溢出和重新加载指令来预先选择寄存器。 预扩展阶段可以减小寄存器压力，使得虚拟寄存器仅通过特定数字超过物理寄存器，虚拟寄存器等于物理寄存器，或者物理寄存器通过特定数量超过实际虚拟寄存器。 编译器然后可以执行一个或多个早期和/或延迟指令调度阶段，包括全局和/或本地指令调度，以优化溢出和重新加载指令的放置。

公开(公告)号：US20110119528A1

公开(公告)日：2011-05-19

申请号：US12618282

申请日：2009-11-13

Applicant: Martin R. Karlsson ,  Sherman H. Yip ,  Shailender Chaudhry

Inventor： Martin R. Karlsson ,  Sherman H. Yip ,  Shailender Chaudhry

IPC: G06F11/00 ,  G06F9/44 ,  G06F7/38

CPC classification number: G06F11/1405

Abstract: The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.

Abstract translation: 所描述的实施例提供用于执行指令的处理器（例如，处理器102）。 在执行期间，处理器通过事先执行来自程序代码的受保护部分的指令来启动。 然后处理器在从程序代码的受保护部分事务地执行指令时遇到事务故障条件。 响应于遇到事务故障条件，处理器进入事务侦察模式并且在事务侦察模式中推测地执行后续指令。

公开(公告)号：US20110107289A1

公开(公告)日：2011-05-05

申请号：US12609370

申请日：2009-10-30

Applicant: Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

Inventor： Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract translation: 在半导体设计中合并门控时钟域的方法和系统包括：对初始的时钟选通功能集合中的时钟门控功能的每个子集产生一组定量的函数，其通过存在量化子集中的每个时钟门控函数产生 一组不是子集的其他时钟门控功能的支持集的一部分的变量。 如果一组量化函数相等，则选择一个作为超时钟门控功能，并将其添加到一组超时钟门控功能。 该超级时钟门控功能集合根据标准进行排序，并选择最佳选项并将其添加到最终时钟门控功能组中。 剩余的超级时钟门控功能被修改，以防止由所选择的超级时钟门控功能选通的触发器被剩余的超时钟门控功能选通。

公开(公告)号：US20110107187A1

公开(公告)日：2011-05-05

申请号：US12611326

申请日：2009-11-03

Applicant: Richard A. Gill ,  Jin Lu

Inventor： Richard A. Gill ,  Jin Lu

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1102 ,  H03M13/27 ,  H04L1/0057 ,  H04L2001/0096

Abstract: An LDPC coding system includes a number of LDPC encoders and a number of LDPC decoders. The number of encoders/decoders is between one and one fewer than the total number of tracks on the high density tape are provided. The LDPC encoders are operable to break data from an incoming data sector into the data blocks to be written to the high density tape. The LDPC decoders are operable to assemble the data blocks into data sectors.

Abstract translation: LDPC编码系统包括多个LDPC编码器和多个LDPC解码器。 编码器/解码器的数量比提供高密度磁带的总轨道数少1到1个。 LDPC编码器可操作以将来自输入数据扇区的数据分解成要写入高密度磁带的数据块。 LDPC解码器可操作以将数据块组装成数据扇区。

公开(公告)号：US20110099175A1

公开(公告)日：2011-04-28

申请号：US12606917

申请日：2009-10-27

Applicant: Joseph D. Darcy

Inventor： Joseph D. Darcy

IPC: G06F17/30

CPC classification number: G06F17/30949

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to implement a “pluperfect” hash function. Generally, a pluperfect hash function is a hash function that maps distinct elements in a set S to distinct hash values H with no collisions (i.e., perfect hash function) and also includes an additional constraint that the hash function does not map other elements outside the set S into the set of distinct hash values H. In some example embodiments, pluperfect hash functions are used to implement a multi-way branch statement in a computer programming language. The implementation may include generating hash values for each of the case labels of the branch statement according to a pluperfect hash function.

Abstract translation: 这里的各种实施例包括用于实现“完美”散列函数的系统，方法，软件和/或数据结构中的一个或多个。 一般来说，一个完整的散列函数是一个散列函数，它将集合S中的不同元素映射到不同的散列值H，没有冲突（即，完美的散列函数），并且还包括一个额外的约束，散列函数不会将其他元素映射到 将S设置为不同的散列值H的集合。在一些示例性实施例中，使用完整的散列函数来实现计算机编程语言中的多路分支语句。 该实现可以包括根据多重散列函数为分支语句的每个案例标签生成哈希值。

公开(公告)号：US20110093731A1

公开(公告)日：2011-04-21

申请号：US12580546

申请日：2009-10-16

Applicant: Alok Parikh ,  Amandeep Singh

Inventor： Alok Parikh ,  Amandeep Singh

IPC: G06F1/28

CPC classification number: G06F11/24

Abstract: Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.

Abstract translation: 本发明的实现可以涉及用于在模拟或测试系统期间同时强调组件的同时改善计算机系统的各个组件的组合功耗和热响应的方法和系统。 一组用于计算机系统的几个单独组件的操作系统级指令集可以设计成在进行功率和热测量时同时施加组件并同时执行。 指令集可以利用计算机系统的一个或多个软件线程或硬件线程，使得当系统被测试时，组件之间的最小干扰发生。 此外，系统组件可以在分开的指令集之间分区。 通过在系统运行时最小化组件之间的干扰，可以在计算机系统上进行更精确的功耗和热效应测量，以更好地近似系统的性能。

公开(公告)号：US20110093251A1

公开(公告)日：2011-04-21

申请号：US12580386

申请日：2009-10-16

Applicant: Kais Belgaied ,  Sunay Tripathi ,  Nicolas G. Droux

Inventor： Kais Belgaied ,  Sunay Tripathi ,  Nicolas G. Droux

IPC: G06F17/50 ,  H04L12/28

CPC classification number: G06F17/509 ,  G06F2009/45595 ,  G06F2217/74 ,  H04L41/12 ,  H04L41/145

Abstract: In general, the invention relates to a creating a network model on a host. The invention includes: gathering first component properties associated with a first physical network device on a target network; creating a first container using first component properties; determining that a second physical network device is operatively connected to the first physical network device via a physical network link; gathering second component properties associated with the physical network link; creating a first VNIC associated with the first container; determining that at least one virtual network device is executing on the second physical network device; gathering third component properties associated with the at least one virtual network device; creating a second container, wherein the second container is configured using the third component properties; and creating a second VNIC associated with the second container.

Abstract translation: 通常，本发明涉及在主机上创建网络模型。 本发明包括：收集与目标网络上的第一物理网络设备相关联的第一组件属性; 使用第一个组件属性创建第一个容器; 确定第二物理网络设备经由物理网络链路可操作地连接到所述第一物理网络设备; 收集与物理网络链接相关联的第二组件属性; 创建与第一容器相关联的第一VNIC; 确定至少一个虚拟网络设备正在所述第二物理网络设备上执行; 收集与所述至少一个虚拟网络设备相关联的第三组件属性; 创建第二容器，其中所述第二容器使用所述第三组分特性构造; 以及创建与所述第二容器相关联的第二VNIC。