公开(公告)号：US08521971B2

公开(公告)日：2013-08-27

申请号：US13443342

申请日：2012-04-10

Applicant: Chun-Kun Lee ,  Wei-Yi Hsiao

Inventor： Chun-Kun Lee ,  Wei-Yi Hsiao

IPC: G06F13/00

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0646 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/7203

Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Abstract translation: 用于管理闪存数据的系统和装置包括主机发送数据，其中当从主机发送的数据具有第一时间传输特性并且数据的地址指示临时地址时，将临时数据从临时地址检索到 外部缓冲区 然后执行写入命令，并且具有目的地地址的临时数据被写入闪存缓冲器。 当闪存缓冲器未满时，缓冲器数据被写入闪速存储器的临时块。 将缓冲器数据写入临时块包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪存缓冲器，使得数据被写入临时块。

公开(公告)号：US08219764B2

公开(公告)日：2012-07-10

申请号：US13069937

申请日：2011-03-23

Applicant: Chun-Kun Lee ,  Wei-Yi Hsiao

Inventor： Chun-Kun Lee ,  Wei-Yi Hsiao

IPC: G06F13/00

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0646 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/7203

Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Abstract translation: 用于管理闪存数据的系统和装置包括主机发送数据，其中当从主机发送的数据具有第一时间传输特性并且数据的地址指示临时地址时，将临时数据从临时地址检索到 外部缓冲区 然后执行写入命令，并且具有目的地地址的临时数据被写入闪存缓冲器。 当闪存缓冲器未满时，缓冲器数据被写入闪速存储器的临时块。 将缓冲器数据写入临时块包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪存缓冲器，使得数据被写入临时块。

公开(公告)号：US20070050534A1

公开(公告)日：2007-03-01

申请号：US11164334

申请日：2005-11-18

Applicant: Lung-Yi Kuo ,  Sheng-I Hsu

Inventor： Lung-Yi Kuo ,  Sheng-I Hsu

IPC: G06F12/00

CPC classification number: G06F11/1068 ,  G11C16/20

Abstract: A method for supporting an unrecognizable flash memory, at least including steps of sending a parameter table comprising strings for error checking to a specified address, checking if the identification is unknown, reading the specified address in the flash memory to determine its cycle if the identification is unknown, checking if the strings for error checking are correctly read, and accessing the system code of the flash memory.

Abstract translation: 一种用于支持不可识别的闪速存储器的方法，至少包括将包括用于错误检查的字符串的参数表发送到指定地址的步骤，检查所述标识是否未知，如果所述标识符识别，读取所述闪存中的指定地址以确定其周期 未知，检查错误检查的字符串是否正确读取，并访问闪存的系统代码。

公开(公告)号：US20110197037A1

公开(公告)日：2011-08-11

申请号：US13092379

申请日：2011-04-22

Applicant: Wu-Chi Kuo

Inventor： Wu-Chi Kuo

IPC: G06F12/00 ,  G06F12/06

CPC classification number: G11C29/28 ,  G11C29/88

Abstract: A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information.

Abstract translation: 提供了用于访问降级存储器和降级存储器设备的方法。 降级存储装置包括至少一个管理单元和控制器。 管理单元包括多个块，每个块具有多个页面，并且每个页面具有多个扇区，降级存储器具有多个不可访问扇区。 控制器被配置为解析对应于特殊块的写入命令，根据特殊块的状态信息来选择至少一个可访问扇区，并且将写入命令编程到特殊块，其中状态信息指示至少一个 不可接触的部门在特别块。 因此，降级存储器的方法和设备可以根据状态信息来省略不可访问扇区以增强使用存储器容量。

公开(公告)号：US07639024B2

公开(公告)日：2009-12-29

申请号：US11595888

申请日：2006-11-13

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G05B24/02 ,  G01R27/02

CPC classification number: H03J7/06 ,  H03H7/25 ,  H03J2200/07 ,  H03K17/687 ,  H03L7/18

Abstract: A resistance compensation circuit and a method thereof for tuning frequency, includes several resistors serially connected to one another, several transistors, each of which connects across one of the corresponding resistances, and a register electrically connected to the gates of the transistors. A control signal controls the switching of the transistors either to compensate the process variation of the resistance through the register or to tune the working frequency of the Integrated circuit.

Abstract translation: 用于调谐频率的电阻补偿电路及其方法包括彼此串联连接的数个电阻器，其中每一个连接到相应电阻中的一个上的几个晶体管，以及电连接到晶体管栅极的寄存器。 控制信号控制晶体管的切换以补偿通过寄存器的电阻的工艺变化或调整集成电路的工作频率。

公开(公告)号：US07512022B2

公开(公告)日：2009-03-31

申请号：US11508248

申请日：2006-08-23

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G11C11/00

CPC classification number: G11C29/832 ,  G11C29/006 ,  G11C29/78

Abstract: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.

Abstract translation: 非易失性存储器阵列结构包括N个位线，M个第一字线，M×N个第一存储器单元，第二字线，n个修复电路和读出放大器。 N位线和M个第一字线被隔行扫描以控制MxN第一存储器单元。 第二个字线被放置在n个位线之间。 每个修复电路电连接在相应的位线和读出放大器之间。 M和N是自然数。

公开(公告)号：US20070247771A1

公开(公告)日：2007-10-25

申请号：US11534244

申请日：2006-09-22

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An analog input/output (I/O) circuit contains a pad, an analog IP (Intellectual Property) circuit, and a transmission gate. The pad is connected to the analog circuit IP. The transmission gate is configured between the pad and analog circuit IP, and therefore any signal between the pad and analog circuit IP must pass through the transmission gate. In normal operation, the transmission gate allows analog signals to transfer between the pad and analog circuit IP. If an ESD (Electrostatic Discharge) current is induced from the pad, the transmission gate discharges the current and protects the analog circuit IP.

Abstract translation: 模拟输入/输出（I / O）电路包含一个焊盘，一个模拟IP（知识产权）电路和一个传输门。 该焊盘连接到模拟电路IP。 传输门被配置在焊盘和模拟电路IP之间，因此焊盘和模拟电路IP之间的任何信号必须通过传输门。 在正常操作中，传输门允许模拟信号在焊盘和模拟电路IP之间传输。 如果从焊盘感应到ESD（静电放电）电流，则传输门放电并保护模拟电路IP。

公开(公告)号：US20070243766A1

公开(公告)日：2007-10-18

申请号：US11443019

申请日：2006-05-31

Applicant: Yu-Ling Hou ,  Hsien-Ming Chang

Inventor： Yu-Ling Hou ,  Hsien-Ming Chang

IPC: H01R24/00

CPC classification number: H05K5/0282 ,  Y10S439/945

Abstract: A memory stick convert device includes an upper housing and lower housing and a convert interface. An assembly of the upper housing and the lower housing has the same type of connector as the Memory Stick (Pro) Duo does at an end. The assembly includes a cavity to accommodate a Micro-SD stick. The convert interface is sandwiched between the upper housing and the lower housing to convert signal formats between the Memory Stick (Pro) Duo and the Micro-SD.

Abstract translation: 记忆棒转换装置包括上壳体和下壳体以及转换界面。 上壳体和下壳体的组件具有与记忆棒（Pro）Duo相同类型的连接器。 组件包括容纳Micro-SD棒的空腔。 转换接口夹在上壳体和下壳体之间，以在Memory Stick（Pro）Duo和Micro-SD之间转换信号格式。

公开(公告)号：US20060131722A1

公开(公告)日：2006-06-22

申请号：US11147430

申请日：2005-06-08

Applicant: Yu-Wei Chyan

Inventor： Yu-Wei Chyan

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A package and a method for saving space required by I/Os of a chip are described. In this method, a plurality of general I/Os and at least one special I/O are allocated in different areas. When the chip is attached to a circuit board, the special I/O is adjacent to a non-soldering area of the circuit board and the general I/Os are adjacent to a soldering area of the circuit board. The special I/O is located on the bottom surface of the chip. When the chip is attached to the circuit board, the special I/O is adjacent to a soldering resistant layer and the general I/Os are electrically connected to signal lines on the circuit board.

Abstract translation: 描述了用于节省芯片的I / O所需的空间的封装和方法。 在该方法中，多个通用I / O和至少一个特殊I / O被分配在不同的区域中。 当芯片连接到电路板上时，特殊I / O与电路板的非焊接区域相邻，并且通用I / O与电路板的焊接区域相邻。 特殊的I / O位于芯片的底面。 当芯片连接到电路板时，特殊I / O与耐焊层相邻，并且通用I / O电连接到电路板上的信号线。

公开(公告)号：US20130311713A1

公开(公告)日：2013-11-21

申请号：US13948613

申请日：2013-07-23

Applicant: SILICONMOTION INC.

Inventor： Chun-Kun LEE ,  Wei-Yi HSIAO

IPC: G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0646 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/7203

Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Abstract translation: 用于管理闪存数据的系统和装置包括主机发送数据，其中当从主机发送的数据具有第一时间传输特性并且数据的地址指示临时地址时，将临时数据从临时地址检索到 外部缓冲区 然后执行写入命令，并且具有目的地地址的临时数据被写入闪存缓冲器。 当闪存缓冲器未满时，缓冲器数据被写入闪速存储器的临时块。 将缓冲器数据写入临时块包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪存缓冲器，使得数据被写入临时块。