公开(公告)号：US20110089535A1

公开(公告)日：2011-04-21

申请号：US12814699

申请日：2010-06-14

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: H01L23/60 ,  H01L29/73

CPC classification number: H01L23/60 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively.

Abstract translation: 本发明提供一种在第一电路和第二电路之间具有ESD路径的静电放电（ESD）保护装置。 静电放电保护器件包括具有第一导电类型的第一掺杂区域。 第一阱具有与第一导电类型相反的第二导电类型。 第一掺杂区和第三掺杂区位于第一阱中，分别具有第一和第二导电类型。 第一掺杂区域耦合到第一电路的电源端子或接地端子，并且第二和第三掺杂区域分别耦合到第二电路的电源端子或接地端子。

公开(公告)号：US07760564B2

公开(公告)日：2010-07-20

申请号：US12379202

申请日：2009-02-17

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G11C11/00

CPC classification number: G11C29/832 ,  G11C29/006 ,  G11C29/78

Abstract: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.

Abstract translation: 非易失性存储器阵列结构包括N位线，M个第一字线，M×N个第一存储器单元，第二字线，n个修复电路和读出放大器。 N位线和M个第一字线被隔行扫描以控制M×N个第一存储单元。 第二个字线被放置在n个位线之间。 每个修复电路电连接在相应的位线和读出放大器之间。 M和N是自然数。

公开(公告)号：US20080073720A1

公开(公告)日：2008-03-27

申请号：US11724194

申请日：2007-03-15

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: H01L23/60

CPC classification number: H01L27/0251

Abstract: An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal.

Abstract translation: 提供了用于在两个电路之间提供ESD路径的静电放电（ESD）保护装置。 每个电路都有一个电源端子和一个接地端子。 保护装置包括等效的MOS，第一端子和第二端子。 等效MOS包括源极，漏极和栅极，其中漏极连接到栅极。 第一个端子连接到门，而第二个端子连接到源。 第一个端子连接到一个电源端子和接地端子，而第二个端子连接到另一个电源端子和接地端子。

公开(公告)号：US20080024146A1

公开(公告)日：2008-01-31

申请号：US11595888

申请日：2006-11-13

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: H01F21/00 ,  G01R27/08

CPC classification number: H03J7/06 ,  H03H7/25 ,  H03J2200/07 ,  H03K17/687 ,  H03L7/18

Abstract: A resistance compensation circuit and a method thereof for tuning frequency, includes several resistors serially connected to one another, several transistors, each of which connects across one of the corresponding resistances, and a register electrically connected to the gates of the transistors. A control signal controls the switching of the transistors either to compensate the process variation of the resistance through the register or to tune the working frequency of the Integrated circuit.

Abstract translation: 用于调谐频率的电阻补偿电路及其方法包括彼此串联连接的数个电阻器，其中每一个连接到相应电阻中的一个上的几个晶体管，以及电连接到晶体管栅极的寄存器。 控制信号控制晶体管的切换以补偿通过寄存器的电阻的工艺变化或调整集成电路的工作频率。

公开(公告)号：US08264479B2

公开(公告)日：2012-09-11

申请号：US12424561

申请日：2009-04-16

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G09G5/00

CPC classification number: G09G5/363 ,  G09G3/36 ,  G09G5/18

Abstract: A display control device for a flat panel display is provided and includes a display controller and a timing controller. The display controller is provided for receiving an input signal and generating a display signal and a plurality of timing signals corresponding to the display signal. The timing controller includes a timing control unit and a data processing unit. The timing control unit is coupled to the display controller for providing a plurality of control signals required for the flat panel display. The data processing unit is incorporated into the display controller in a first integrated circuit chip for receiving the display signal and generating a plurality of output signals in synchronization with the timing signals. The output signals are output to the flat panel display through a predetermined interface.

Abstract translation: 提供了一种用于平板显示器的显示控制装置，包括显示控制器和定时控制器。 显示控制器用于接收输入信号并产生显示信号和对应于显示信号的多个定时信号。 定时控制器包括定时控制单元和数据处理单元。 定时控制单元耦合到显示控制器，用于提供平板显示器所需的多个控制信号。 在第一集成电路芯片中将数据处理单元并入显示控制器中，用于接收显示信号并与定时信号同步地产生多个输出信号。 输出信号通过预定接口输出到平板显示器。

公开(公告)号：US07608894B2

公开(公告)日：2009-10-27

申请号：US11724194

申请日：2007-03-15

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: H01L23/62

CPC classification number: H01L27/0251

Abstract: An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal.

Abstract translation: 提供了用于在两个电路之间提供ESD路径的静电放电（ESD）保护装置。 每个电路都有一个电源端子和一个接地端子。 保护装置包括等效的MOS，第一端子和第二端子。 等效MOS包括源极，漏极和栅极，其中漏极连接到栅极。 第一个端子连接到门，而第二个端子连接到源。 第一个端子连接到一个电源端子和接地端子，而第二个端子连接到另一个电源端子和接地端子。

公开(公告)号：US20080315854A1

公开(公告)日：2008-12-25

申请号：US12038042

申请日：2008-02-27

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G05F3/08

CPC classification number: H01L27/0251

Abstract: An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof.

Abstract translation: 提供了一个I / O调节电路。 I / O调节电路在CMOS工艺中省略了ESD器件，具有最小化的临界尺寸，以减少芯片尺寸，同时仍然保持静电放电抗扰性。 I / O调节电路应用于MLC闪存应用及其闪存控制器。

公开(公告)号：US20070297230A1

公开(公告)日：2007-12-27

申请号：US11508248

申请日：2006-08-23

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G11C16/06 ,  G11C29/00 ,  G11C11/34 ,  G11C7/02 ,  G11C7/00

CPC classification number: G11C29/832 ,  G11C29/006 ,  G11C29/78

Abstract: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.

Abstract translation: 非易失性存储器阵列结构包括N个位线，M个第一字线，M×N个第一存储器单元，第二字线，n个修复电路和读出放大器。 N位线和M个第一字线被隔行扫描以控制MxN第一存储器单元。 第二个字线被放置在n个位线之间。 每个修复电路电连接在相应的位线和读出放大器之间。 M和N是自然数。

公开(公告)号：US20070040220A1

公开(公告)日：2007-02-22

申请号：US11163772

申请日：2005-10-29

Applicant: Te-Wei Chen ,  Li-Chiu Weng

Inventor： Te-Wei Chen ,  Li-Chiu Weng

IPC: H01L23/62

CPC classification number: H01L27/0255

Abstract: An electrostatic discharge circuit includes at least an electrostatic discharge zener diode, an NMOS transistor, and a PMOS transistor. The electrostatic discharge zener diode is used for lowering the breakdown voltage and making the electrical current discharge through it, thereby preventing the circuit device from burning out and greatly enhancing the function of electrostatic discharge protection.

Abstract translation: 静电放电电路至少包括静电放电齐纳二极管，NMOS晶体管和PMOS晶体管。 静电放电齐纳二极管用于降低击穿电压并使电流通过其放电，从而防止电路器件烧坏并大大提高静电放电保护功能。

公开(公告)号：US06465864B2

公开(公告)日：2002-10-15

申请号：US09793945

申请日：2001-02-27

Applicant: Te-Wei Chen ,  Jia Jio Huang

Inventor： Te-Wei Chen ,  Jia Jio Huang

IPC: H01L2900

CPC classification number: H01L27/0814 ,  H01L29/167 ,  H01L29/8611

Abstract: Three diode structures on a metal-oxide-semiconductor (MOS) wafer. Each diode structure is capable of reducing parasitic current through the wafer and hence increasing the power conversion efficiency of a voltage step-up circuit.

Abstract translation: 金属氧化物半导体（MOS）晶片上的三个二极管结构。 每个二极管结构能够减小通过晶片的寄生电流，从而提高升压电路的功率转换效率。