公开(公告)号：US5260868A

公开(公告)日：1993-11-09

申请号：US776713

申请日：1991-10-15

Applicant: Subhash Gupta ,  Sanjiv S. Sidhu ,  Frank Vlach

Inventor： Subhash Gupta ,  Sanjiv S. Sidhu ,  Frank Vlach

IPC: G05B19/418 ,  G06Q10/06 ,  G07C3/00 ,  G06F15/20

CPC classification number: G06Q10/06 ,  G05B19/41865 ,  G07C3/00 ,  G05B2219/34418 ,  Y02P90/20

Abstract: A mechanism and method for calendaring a plurality of events such as scheduling the operation of interrelated machines which perform a process flow. Future time is divided into segments, called buckets, of increasing length. The first two buckets are of the same size and each of the following buckets twice as large as its preceding bucket. The first bucket slides so as to always cover a specified length of time following the current time. Events scheduled in the calendar is added to the appropriate bucket, depending on how far in the future it is to take place. When the current time equals the scheduled time for an event, then that event is removed from the bucket where it resides. When a bucket has become empty because all events have been removed from it, the events in the following bucket are distributed over the two buckets preceding it.

Abstract translation: 一种用于对多个事件进行日历的机制和方法，例如调度执行处理流程的相互关联的机器的操作。 未来时间被分为长度增长的段，称为桶。 前两个桶的尺寸相同，以下桶中的每一个都是前一桶的两倍。 第一个铲斗滑动，以便在当前时间之后始终覆盖指定的时间长度。 日程安排的活动将添加到相应的存储桶中，具体取决于将来发生的时间。 当当前时间等于事件的预定时间时，该事件将从它驻留的存储桶中删除。 当桶已经变为空时，因为所有事件都已从其中删除，下一个桶中的事件将分布在其前面的两个桶中。

公开(公告)号：US11755046B2

公开(公告)日：2023-09-12

申请号：US17353387

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

CPC classification number: G05F1/571 ,  G05F1/59 ,  G05F3/24

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.