公开(公告)号：US08643397B2

公开(公告)日：2014-02-04

申请号：US13245504

申请日：2011-09-26

Applicant: Hsin-Ming Hou ,  Ji-Fu Kung

Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

IPC: G01R31/02

CPC classification number: G01R31/27 ,  G01R31/2884

Abstract: A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.

Abstract translation: 提供了用于测试的晶体管阵列。 晶体管阵列包括多个测试单元。 每个测试单元包括测试晶体管和第一至第三开关。 经测试的晶体管具有控制端子，第一和第二端子和体积。 第一开关耦合在第一端子和泄漏输送线之间。 第二开关连接在第二端子和泄漏输送线之间。 第三开关耦合在控制端和偏压提供线之间。 第一至第三开关根据控制信号导通或关断。 当测试晶体管被选择进行测试时，第一至第三开关根据控制信号导通。

公开(公告)号：US10475932B2

公开(公告)日：2019-11-12

申请号：US15828060

申请日：2017-11-30

Applicant: United Microelectronics Corp.

Inventor： Shao-Hui Wu ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8258

Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.

公开(公告)号：US09780169B2

公开(公告)日：2017-10-03

申请号：US14876844

申请日：2015-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Yu-Cheng Tung ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.