利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.009 秒)

    Unambiguous digital processing of dual binary three-valued codes
    5.
    发明授权
    Unambiguous digital processing of dual binary three-valued codes 失效

    公开(公告)号：US3641327A

    公开(公告)日：1972-02-08

    申请号：US3641327D

    申请日：1969-08-13

    申请人： CARL W NELSON JR

    发明人： NELSON CARL W JR

    IPC分类号： H04L9/18 ,  G06F5/02

    CPC分类号： H03M5/04 ,  G06F7/405

    摘要： This invention contemplates means for digital resolution of three-valued code ambiguities resulting from the combination in parallel of two signed binary sequences (O -, 1 +, or vice versa) offset from one another by one-half code element, their combination relating elements of the second to adjacent elements of the first and resulting in three-valued code elements+, 0 or , the first three-valued code sequence element being ambiguous due to the signed binary sequences'' offset, said first element three-valued ambiguity being resolved by combining the signed value of the final element in the second signed binary sequence with the signed value of the first element in the first binary sequence; and, the last three-valued code sequence also being ambiguous due to the signed binary sequences'' offset, said last element three-valued ambiguity being resolved by repeating the signed value of the final element in the second signed binary sequence as an appended final signed value in the resulting three-valued sequence, said appended final three-valued sequence element being called the LINK; the inherent nonredundant error detection feature of this class of three-valued codes being preserved; the LINK providing information and means for unambiguous decoding of the said three-valued sequence, zero value elements of which are ambiguous and all-zero value threevalued sequences being totally ambiguous in decode to the two component signed binary sequences, the said decode ambiguities being resolved by circuit means to place the signed value of the three-valued LINK element into the last element of the second signed binary sequence, in turn the last element of the second signed binary sequence being combined with the next to the last three-valued sequence thus defining the signed value of the last element in the first signed binary sequence, circuit operations being carried on sequentially to finally produce the first elements of the signed binary sequences and a FLAG signal element useful in clocking the signed bnary binary into their related circuit registers.