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    In-order traffic aggregation with reduced buffer usage
    1.
    发明授权
    In-order traffic aggregation with reduced buffer usage 有权
    降低缓冲区使用率的按顺序流量聚合

    公开(公告)号：US09137166B2

    公开(公告)日：2015-09-15

    申请号：US12695401

    申请日：2010-01-28

    申请人： Daniel Sangyoung Lee ,  Yuen Fai Wong

    发明人： Daniel Sangyoung Lee ,  Yuen Fai Wong

    IPC分类号： H04L12/801

    CPC分类号： H04L47/34

    摘要： One embodiment provides a system that performs in-order traffic aggregation from a number of low-speed ports to a high-speed port. During operation, the system receives at a low-speed port a packet, stores it in a store-and-forward FIFO associated with the low-speed port, extracts a sequence number associated with the stored packet, and stores the extracted sequence number in a sequence-number FIFO associated with the low-speed port. The system further generates an expected sequence number, which maintains a linear order with respect to sequence numbers associated with previously forwarded packets, and determines whether a front end of the sequence-number FIFO matches the expected sequence number. If so, the system removes the front end of the sequence-number FIFO buffer, retrieves a packet associated with it, forwards the retrieved packet on the high-speed port, and updates the expected sequence number by adding 1 to the packet number of the retrieved packet.

    摘要翻译： 一个实施例提供一种执行从多个低速端口到高速端口的按顺序流量聚合的系统。 在操作期间，系统在低速端口接收到一个数据包，将其存储在与低速端口相关联的存储转发FIFO中，提取与存储的数据包相关联的序列号，并将提取的序列号存储在 与低速端口相关联的序列号FIFO。 该系统进一步产生预期序列号，该序列号相对于与先前转发的分组相关联的序列号保持线性顺序，并且确定序列号FIFO的前端是否与期望的序列号匹配。 如果是这样，系统删除序列号FIFO缓冲区的前端，检索与之相关联的数据包，在高速端口转发检索到的数据包，并通过将预期序列号加1来更新预期序列号 检索包。

    System and method for high speed packet transmission
    2.
    发明授权
    System and method for high speed packet transmission 有权
    高速数据包传输的系统和方法

    公开(公告)号：US08811390B2

    公开(公告)日：2014-08-19

    申请号：US12608972

    申请日：2009-10-29

    申请人： Yuen Fai Wong

    发明人： Yuen Fai Wong

    IPC分类号： H04L12/50 ,  H04Q11/04 ,  H04L12/56

    CPC分类号： H04L49/352 ,  H04L5/14 ,  H04L12/4645 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/30 ,  H04L49/3063 ,  H04Q11/0428

    摘要： The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

    摘要翻译： 本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。 根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。 该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理 并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。 第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。 耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。 第三个FPGA进一步操作以从背板接收和分发分组。

    Method and apparatus for aggregating input data streams
    4.
    发明授权
    Method and apparatus for aggregating input data streams 有权

    公开(公告)号：US08493988B2

    公开(公告)日：2013-07-23

    申请号：US12880518

    申请日：2010-09-13

    申请人： Yuen Fai Wong ,  Yu-Mei Lin ,  Richard A. Grenier

    发明人： Yuen Fai Wong ,  Yu-Mei Lin ,  Richard A. Grenier

    IPC分类号： H04L12/28

    CPC分类号： H04L47/2433 ,  H04L47/6275 ,  H04L49/30 ,  H04L49/352

    摘要： A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

    HIGH SPEED COUNTER DESIGN
    6.
    发明申请
    HIGH SPEED COUNTER DESIGN 有权
    高速计数器设计

    公开(公告)号：US20120166760A1

    公开(公告)日：2012-06-28

    申请号：US12271394

    申请日：2008-11-14

    申请人： Yuen Fai Wong ,  Hui Zhang

    发明人： Yuen Fai Wong ,  Hui Zhang

    IPC分类号： G06F12/06

    CPC分类号： G06F7/5055

    摘要： Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater.

    摘要翻译： 以有效的方式增加计数器的技术。 在一组实施例中，提供了可以以比现有计数器逻辑电路更高的频率工作的计数器逻辑电路，同时能够在当前可用的现场可编程门阵列（FPGA）中实现或者使用当前可用的处理技术制造。 本发明的计数器逻辑电路可用于增加支持40Gbps，100Gbps和更高线路速度的网络设备中的统计计数器。

    SOURCE-BASED CONGESTION DETECTION AND CONTROL
    8.
    发明申请
    SOURCE-BASED CONGESTION DETECTION AND CONTROL 有权
    基于源的控制检测与控制

    公开(公告)号：US20110235518A1

    公开(公告)日：2011-09-29

    申请号：US13156145

    申请日：2011-06-08

    申请人： Mitri Halabi ,  Yuen Fai Wong ,  Robert Colvin ,  Frank S. Yang

    发明人： Mitri Halabi ,  Yuen Fai Wong ,  Robert Colvin ,  Frank S. Yang

    IPC分类号： H04L12/26

    CPC分类号： H04L47/30 ,  H04L47/263

    摘要： Congestion control techniques based upon resource utilization information stored by a network device. According to an embodiment of the present invention, a network device is configured to identify a data source causing congestion based upon information stored by the network device identifying a set of data sources, and for each data source, information identifying the amount of a resource of the network device being used for processing data received by the network device from the data source.

    摘要翻译： 基于由网络设备存储的资源利用信息的拥塞控制技术。 根据本发明的实施例，网络设备被配置为基于识别一组数据源的网络设备存储的信息来识别引起拥塞的数据源，并且对于每个数据源，标识资源的量的信息 所述网络设备用于处理由所述网络设备从所述数据源接收的数据。

    IN-ORDER TRAFFIC AGGREGATION WITH REDUCED BUFFER USAGE
    9.
    发明申请
    IN-ORDER TRAFFIC AGGREGATION WITH REDUCED BUFFER USAGE 有权
    使用减少缓冲区的订单交付聚合

    公开(公告)号：US20110182294A1

    公开(公告)日：2011-07-28

    申请号：US12695401

    申请日：2010-01-28

    申请人： Daniel Sangyoung Lee ,  Yuen Fai Wong

    发明人： Daniel Sangyoung Lee ,  Yuen Fai Wong

    IPC分类号： H04L12/56

    CPC分类号： H04L47/34

    摘要： One embodiment provides a system that performs in-order traffic aggregation from a number of low-speed ports to a high-speed port. During operation, the system receives at a low-speed port a packet, stores it in a store-and-forward FIFO associated with the low-speed port, extracts a sequence number associated with the stored packet, and stores the extracted sequence number in a sequence-number FIFO associated with the low-speed port. The system further generates an expected sequence number, which maintains a linear order with respect to sequence numbers associated with previously forwarded packets, and determines whether a front end of the sequence-number FIFO matches the expected sequence number. If so, the system removes the front end of the sequence-number FIFO buffer, retrieves a packet associated with it, forwards the retrieved packet on the high-speed port, and updates the expected sequence number by adding 1 to the packet number of the retrieved packet.

    摘要翻译： 一个实施例提供一种执行从多个低速端口到高速端口的按顺序流量聚合的系统。 在操作期间，系统在低速端口接收到一个数据包，将其存储在与低速端口相关联的存储转发FIFO中，提取与存储的数据包相关联的序列号，并将提取的序列号存储在 与低速端口相关联的序列号FIFO。 该系统进一步产生预期序列号，该序列号相对于与先前转发的分组相关联的序列号保持线性顺序，并且确定序列号FIFO的前端是否与期望的序列号匹配。 如果是这样，系统删除序列号FIFO缓冲区的前端，检索与之相关联的数据包，在高速端口转发检索到的数据包，并通过将预期序列号加1来更新预期序列号 检索包。

    Source-based congestion detection and control
    10.
    发明授权
    Source-based congestion detection and control 有权
    基于源的拥塞检测和控制

    公开(公告)号：US07978607B1

    公开(公告)日：2011-07-12

    申请号：US12412290

    申请日：2009-03-26

    申请人： Mitri Halabi ,  Yuen Fai Wong ,  Robert Colvin ,  Frank S. Yang

    发明人： Mitri Halabi ,  Yuen Fai Wong ,  Robert Colvin ,  Frank S. Yang

    IPC分类号： H04J1/16

    CPC分类号： H04L47/30 ,  H04L47/263

    摘要： Congestion control techniques based upon resource utilization information stored by a network device. According to an embodiment of the present invention, a network device is configured to identify a data source causing congestion based upon information stored by the network device identifying a set of data sources, and for each data source, information identifying the amount of a resource of the network device being used for processing data received by the network device from the data source.

    摘要翻译： 基于由网络设备存储的资源利用信息的拥塞控制技术。 根据本发明的实施例，网络设备被配置为基于识别一组数据源的网络设备存储的信息来识别引起拥塞的数据源，并且对于每个数据源，标识资源的量的信息 所述网络设备用于处理由所述网络设备从所述数据源接收的数据。