公开(公告)号：US20030187894A1

公开(公告)日：2003-10-02

申请号：US10106549

申请日：2002-03-27

申请人： Broadcom Corporation

发明人： Minsheng Wang

IPC分类号： G06F017/17

CPC分类号： H03H17/0279 ,  H03H17/0664 ,  H03H17/0671

摘要： A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)null(1nullznull1)N, where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an Nth-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor IL.

摘要翻译： 一种抽取系统，包括多个级联的有限脉冲响应（FIR）抽取滤波器。 每个抽取滤波器具有H（z）=（1 + z -1）N形式的传递函数，其中N是整数。 每个FIR抽取滤波器通过公共因子I执行抽取。级联FIR抽取滤波器一起实现与执行N次级CIC滤波器（即，具有N个积分器级的CIC滤波器）基本相同的抽取结果，其执行 抽取因子I 。

公开(公告)号：US06392576B1

公开(公告)日：2002-05-21

申请号：US09935095

申请日：2001-08-21

申请人： Gerald Wilson ,  Robert S. Green

发明人： Gerald Wilson ,  Robert S. Green

IPC分类号： H03M300

CPC分类号： H03H17/0225 ,  H03H17/0279 ,  H03H17/0285 ,  H03H17/0416 ,  H03H17/0444

摘要： A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

摘要翻译： 提出了一种用于数字信号插值的简化算法和一种在具有显着空间约束的集成电路（“IC”）中实现该算法的新型架构。 根据本发明的实施例，内插器被分成两部分。 插值器的第一部分将采样率提高一倍，并使用半带无限脉冲响应（“IIR”）滤波器对信号进行平滑。 内插器的第二部分使用零级保持（“ZOH”）电路将信号的采样率增加了三十二倍。 在一个实施例中，使用全通格格结构来实现半带IIR滤波器以使量化效应最小化。 选择晶格系数使得该结构可以实现所有滤波器设计要求，但是能够用少量的移位器和加法器实现，并且不需要乘法器。

公开(公告)号：US07010557B2

公开(公告)日：2006-03-07

申请号：US10106549

申请日：2002-03-27

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： G06F17/17

CPC分类号： H03H17/0279 ,  H03H17/0664 ,  H03H17/0671

摘要： A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)=(1+z−1)N, where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an Nth-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor IL.

摘要翻译： 一种抽取系统，包括多个级联的有限脉冲响应（FIR）抽取滤波器。 每个抽取滤波器具有形式为H（z）=（1 + z 0 - 1）的传递函数，其中N是整数。 每个FIR抽取滤波器通过公共因子I执行抽取。级联FIR抽取滤波器一起实现与第N个次级CIC滤波器（即，具有N个N个CIC滤波器的CIC滤波器）基本相同的抽取结果 积分器级），其通过因子I ^{L执行抽取。}

公开(公告)号：US09037625B2

公开(公告)日：2015-05-19

申请号：US13441501

申请日：2012-04-06

申请人： Mark Alan Sturza ,  Donald Leimer

发明人： Mark Alan Sturza ,  Donald Leimer

IPC分类号： H03H17/02 ,  H03H17/06

CPC分类号： H03H17/0279 ,  H03H17/0277 ,  H03H17/0664

摘要： A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

摘要翻译： 提供了一种用于将数字信号抽取为因子M并将其与所需信道带宽匹配的方法。 该方法将数字信号输入采样应用于（M-1）级抽头延迟线，将每个抽头延迟线级的输入采样和输出采样下降一个因子M，并将每个M下采样的采样值流 到M allpass IIR滤波器。 然后将M allpass IIR滤波后的样本流相加并按比例乘以1 / M。 然后可以通过数字通道滤波器对结果进行滤波。

公开(公告)号：US08176107B2

公开(公告)日：2012-05-08

申请号：US11611542

申请日：2006-12-15

申请人： Mark Alan Sturza ,  Donald Leimer

发明人： Mark Alan Sturza ,  Donald Leimer

IPC分类号： G06F17/17

CPC分类号： H03H17/0279 ,  H03H17/0277 ,  H03H17/0664

摘要： A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M-1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

摘要翻译： 提供了一种用于将数字信号抽取为因子M并将其与所需信道带宽匹配的方法。 该方法将数字信号输入采样应用于（M-1）级抽头延迟线，将每个抽头延迟线级的输入采样和输出采样下降一个因子M，并将每个M下采样的采样值流 到M allpass IIR滤波器。 然后将M allpass IIR滤波后的样本流相加并按比例乘以1 / M。 然后可以通过数字通道滤波器对结果进行滤波。

公开(公告)号：US06313773B1

公开(公告)日：2001-11-06

申请号：US09491695

申请日：2000-01-26

申请人： Gerald Wilson ,  Robert S. Green

发明人： Gerald Wilson ,  Robert S. Green

IPC分类号： H03M300

CPC分类号： H03H17/0225 ,  H03H17/0279 ,  H03H17/0285 ,  H03H17/0416 ,  H03H17/0444

摘要： A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

摘要翻译： 提出了一种用于数字信号插值的简化算法和一种在具有显着空间约束的集成电路（“IC”）中实现该算法的新型架构。 根据本发明的实施例，内插器被分成两部分。 插值器的第一部分将采样率提高一倍，并使用半带无限脉冲响应（“IIR”）滤波器对信号进行平滑。 内插器的第二部分使用零级保持（“ZOH”）电路将信号的采样率增加了三十二倍。 在一个实施例中，使用全通格格结构来实现半带IIR滤波器以使量化效应最小化。 选择晶格系数使得该结构可以实现所有滤波器设计要求，但是能够用少量的移位器和加法器实现，并且不需要乘法器。

公开(公告)号：US4908787A

公开(公告)日：1990-03-13

申请号：US894994

申请日：1986-08-08

申请人： Nigel P. Dyer

发明人： Nigel P. Dyer

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/04 ,  H03H17/08

CPC分类号： H03H17/0279 ,  H03H17/025 ,  H03H17/0444 ,  H03H17/045

摘要： A filter structure including a notch filter is designed to have a transmission zero at a frequency slightly displaced from one half of the lower sampling rate of the interpolator/decimator, and thus providing increase in attenuation at the half-rate frequency. The notch filter is comprised of two like all-pass-network filters and has feed forward and feedback connections, the latter connection including a coefficient multiplier. The feedback connection is made between a tapped output of the second of the network filters and an input node. The tapped filter is characterized by throughput and a tapped output transform functions X(Z) and Y(Z) given by the following expressions:X(Z)=[Z.sup.-1 -K]/[1-KZ.sup.-1 ; and,Y(Z)=.alpha.Z.sup.-1 /[1-KZ.sup.-1 ;where Z.sup.-1 is the unit delay operator, K the multiplier coefficient and, .alpha., a structure dependant constant.

摘要翻译： 包括陷波滤波器的滤波器结构被设计为具有在内插器/抽取器的较低采样率的一半稍微偏移的频率处的传输零点，并且因此提供在半速率频率处的衰减增加。 陷波滤波器由两个像全通滤波器组成，并具有前馈和反馈连接，后一连接包括一个系数乘法器。 反馈连接在第二个网络过滤器的抽头输出和输入节点之间进行。 抽头滤波器的特征在于以下表达式给出的吞吐量和抽头输出变换函数X（Z）和Y（Z）：X（Z）= [Z-1-K] / [1-KZ-1; 和Y（Z）=αZ-1 / [1-KZ-1; 其中Z-1是单位延迟算子，K是乘数系数，α是结构依赖常数。

公开(公告)号：US20120254272A1

公开(公告)日：2012-10-04

申请号：US13441501

申请日：2012-04-06

申请人： Mark Alan Sturza ,  Donald Leimer

发明人： Mark Alan Sturza ,  Donald Leimer

IPC分类号： G06F17/17

CPC分类号： H03H17/0279 ,  H03H17/0277 ,  H03H17/0664

摘要： A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

摘要翻译： 提供了一种用于将数字信号抽取为因子M并将其与所需信道带宽匹配的方法。 该方法将数字信号输入采样应用于（M-1）级抽头延迟线，将每个抽头延迟线级的输入采样和输出采样下降一个因子M，并将每个M下采样的采样值流 到M allpass IIR滤波器。 然后将M allpass IIR滤波后的样本流相加并按比例乘以1 / M。 然后可以通过数字通道滤波器对结果进行滤波。

公开(公告)号：US20080133224A1

公开(公告)日：2008-06-05

申请号：US11565342

申请日：2006-11-30

申请人： Hongwei Kong ,  Huaiyu Zeng ,  Nelson Sollenberger ,  Li Fung Chang

发明人： Hongwei Kong ,  Huaiyu Zeng ,  Nelson Sollenberger ,  Li Fung Chang

IPC分类号： G10L19/00

CPC分类号： H03H17/04 ,  G10L19/173 ,  H03H17/0279 ,  H03H17/0444 ,  H03H17/06

摘要： Methods and systems for processing multipath, multi-rate digital audio signals are disclosed herein. Aspects of the method may comprise up-sampling a number of digital audio signals and converting the up-sampled digital audio signals to a common data rate prior to mixing. The digital audio signals sampling rates may be converted utilizing half-band interpolators. The up-sampling may also utilize infinite impulse response interpolators. A portion of the up-sampled digital audio signals may have a common data rate. The common data rate may be determined by the number half-band interpolators utilized. Distortion in the digital audio signals may be compensated utilizing an infinite impulse response filter or a finite impulse response filter.

摘要翻译： 本文公开了用于处理多路径，多速率数字音频信号的方法和系统。 方法的方面可以包括对多个数字音频信号进行上采样，并将上采样的数字音频信号在混合之前转换成公共数据速率。 可以使用半带内插器来转换数字音频信号采样率。 上采样也可以利用无限脉冲响应内插器。 上采样的数字音频信号的一部分可以具有公共数据速率。 公共数据速率可以由所使用的数量半带内插器来确定。 可以使用无限脉冲响应滤波器或有限脉冲响应滤波器来补偿数字音频信号中的失真。

公开(公告)号：US20070156800A1

公开(公告)日：2007-07-05

申请号：US11611542

申请日：2006-12-15

申请人： Mark Sturza ,  Donald Leimer

发明人： Mark Sturza ,  Donald Leimer

IPC分类号： G06F17/10

CPC分类号： H03H17/0279 ,  H03H17/0277 ,  H03H17/0664

摘要： A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IRR filters, respectively. The M allpass IRR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

摘要翻译： 提供了一种用于将数字信号抽取为因子M并将其与所需信道带宽匹配的方法。 该方法将数字信号输入采样应用于（M-1）级抽头延迟线，将每个抽头延迟线级的输入采样和输出采样下降一个因子M，并将每个M下采样的采样值流 到M allpass IRR滤波器。 然后将M allpass IRR滤波的样本流相加并按比例乘以1 / M。 然后可以通过数字通道滤波器对结果进行滤波。