公开(公告)号：US06392576B1

公开(公告)日：2002-05-21

申请号：US09935095

申请日：2001-08-21

Applicant: Gerald Wilson ,  Robert S. Green

Inventor： Gerald Wilson ,  Robert S. Green

IPC: H03M300

CPC classification number: H03H17/0225 ,  H03H17/0279 ,  H03H17/0285 ,  H03H17/0416 ,  H03H17/0444

Abstract: A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

Abstract translation: 提出了一种用于数字信号插值的简化算法和一种在具有显着空间约束的集成电路（“IC”）中实现该算法的新型架构。 根据本发明的实施例，内插器被分成两部分。 插值器的第一部分将采样率提高一倍，并使用半带无限脉冲响应（“IIR”）滤波器对信号进行平滑。 内插器的第二部分使用零级保持（“ZOH”）电路将信号的采样率增加了三十二倍。 在一个实施例中，使用全通格格结构来实现半带IIR滤波器以使量化效应最小化。 选择晶格系数使得该结构可以实现所有滤波器设计要求，但是能够用少量的移位器和加法器实现，并且不需要乘法器。

公开(公告)号：US06313773B1

公开(公告)日：2001-11-06

申请号：US09491695

申请日：2000-01-26

Applicant: Gerald Wilson ,  Robert S. Green

Inventor： Gerald Wilson ,  Robert S. Green

IPC: H03M300

CPC classification number: H03H17/0225 ,  H03H17/0279 ,  H03H17/0285 ,  H03H17/0416 ,  H03H17/0444

Abstract: A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

Abstract translation: 提出了一种用于数字信号插值的简化算法和一种在具有显着空间约束的集成电路（“IC”）中实现该算法的新型架构。 根据本发明的实施例，内插器被分成两部分。 插值器的第一部分将采样率提高一倍，并使用半带无限脉冲响应（“IIR”）滤波器对信号进行平滑。 内插器的第二部分使用零级保持（“ZOH”）电路将信号的采样率增加了三十二倍。 在一个实施例中，使用全通格格结构来实现半带IIR滤波器以使量化效应最小化。 选择晶格系数使得该结构可以实现所有滤波器设计要求，但是能够用少量的移位器和加法器实现，并且不需要乘法器。

公开(公告)号：US4740906A

公开(公告)日：1988-04-26

申请号：US646381

申请日：1984-08-31

Applicant: Karl H. Renner ,  Alec J. Morton

Inventor： Karl H. Renner ,  Alec J. Morton

IPC: G10L19/06 ,  G06F7/544 ,  G06F17/10 ,  G10L11/00 ,  G10L19/04 ,  H03H17/02 ,  G06F15/31 ,  G10L1/00

CPC classification number: H03H17/0285 ,  G06F7/5443

Abstract: A lattice filter for processing lattice equations includes a fast adder (78) for adding partial products to partially perform a multiplication step. A full adder (44) is provided for completing the multiplication and then adding the product with a previously calculated and stored value. The input to the full adder (44) is multiplexed with a multiplexer (74) for selecting the sum output of the fast adder (78) and a multiplexer (76) for selecting the carry output of the fast adder (78). The multiplexer (74) also selects prestored values for addition with the summed output of the full adder (44). This summed output is selected by the multiplexer (76). The fast adder (78) sums partial products simultaneous with addition operations of the full adder (44). In this manner, the full adder (44) operates at a slower rate than the fast adder (78). Storage registers (58), (62), (70) are utilized to delay results output by the full adder (44) for later selection and operation thereon. These values are utilized as both the multiplicand the addend in subsequent operations. The multiplier is stored in a K-stack (90) and selected for the appropriate operations. A bit correction circuit (190) provides corrections for truncated bits in the form of a carry input to the full adder (44).

Abstract translation: 用于处理晶格方程的晶格滤波器包括用于部分地执行乘法步骤的部分乘积的快速加法器（78）。 提供一个完整加法器（44）用于完成乘法，然后将乘积与先前计算和存储的值相加。 对全加器（44）的输入与用于选择快速加法器（78）的和输出的复用器（74）和用于选择快速加法器（78）的进位输出的多路复用器（76）复用。 多路复用器（74）还用全加器（44）的相加输出选择用于相加的预存值。 该相加输出由多路复用器（76）选择。 快速加法器（78）将全部加法器（44）的加法运算同时产生部分乘积。 以这种方式，全加器（44）以比快速加法器（78）更慢的速率工作。 存储寄存器（58），（62），（70）用于延迟由全加器（44）输出的结果，用于其后的选择和操作。 这些值被用作后续操作中的被乘数加数。 乘法器存储在K堆栈（90）中，并进行适当的操作。 位校正电路（190）以对进位输入的形式对全加器（44）提供校正。

公开(公告)号：US4389539A

公开(公告)日：1983-06-21

申请号：US242191

申请日：1981-03-10

Applicant: Taisuke Watanabe ,  Katsuyuki Niyada ,  Shoji Hiraoka ,  Kenji Kaga

Inventor： Taisuke Watanabe ,  Katsuyuki Niyada ,  Shoji Hiraoka ,  Kenji Kaga

IPC: G10L19/06 ,  G10L11/00 ,  G10L19/00 ,  H03H17/00 ,  H03H17/02 ,  G10L1/00

CPC classification number: H03H17/0285 ,  G10L19/00

Abstract: A single section digital filter is provided with a digital input signal and includes a serial multiplier having an input responsive to predetermine parameters. An adder/subtractor has an input serially connected to the multiplier output. A first switch serially selects recirculating data from an adder/subtractor output directly or delayed, or the digital input signal. A second input of the multiplier is serially provided with the selected data. A second switch serially and selectively connects delayed selected data to a second input of the adder/subtractor. A latch serially receives delayed data for effecting series/parallel conversion thereof.

Abstract translation: 单区数字滤波器具有数字输入信号，并且包括具有响应于预定参数的输入的串行乘法器。 加法器/减法器具有串联连接到乘法器输出的输入。 第一开关从直接或延迟的加法器/减法器输出或数字输入信号串行地选择再循环数据。 乘法器的第二个输入与所选数据串行提供。 第二开关串行和选择地将延迟选择的数据连接到加法器/减法器的第二输入端。 锁存器串行地接收用于进行其串/并转换的延迟数据。

公开(公告)号：US20120185525A1

公开(公告)日：2012-07-19

申请号：US13265288

申请日：2010-12-04

Applicant: Satya Sudhakar Yedlapalli ,  Kuchibhotla Venkata Subrahmanya Hari

Inventor： Satya Sudhakar Yedlapalli ,  Kuchibhotla Venkata Subrahmanya Hari

IPC: G06F17/10

CPC classification number: H03H17/025 ,  G01S1/76 ,  G01S3/805 ,  H03H17/0285 ,  H03H2017/0298 ,  H03H2218/04

Abstract: Various techniques are generally described for digital signal processing (DSP) such as discrete time filters. In some examples, a Canonic Filter Module (CFM) can be used to configure the discrete time filter using an LSF-Model with a finite length sequence. A single CFM can be configured to provide any type of discrete time filter used in signal processing. Filters can be modeled as a set of interconnected notch filters, a lattice structure of a discrete time filter is generally described that is based on a LSF-Model.

Abstract translation: 通常描述用于诸如离散时间滤波器的数字信号处理（DSP）的各种技术。 在一些示例中，可以使用Canonic Filter Module（CFM）来配置具有有限长度序列的LSF-Model的离散时间过滤器。 单个CFM可以配置为提供用于信号处理的任何类型的离散时间滤波器。 滤波器可以被建模为一组互连的陷波滤波器，通常描述基于LSF模型的离散时间滤波器的格子结构。

公开(公告)号：US5587910A

公开(公告)日：1996-12-24

申请号：US384084

申请日：1995-02-06

Applicant: Jeffrey P. Woodard

Inventor： Jeffrey P. Woodard

IPC: G06F17/40 ,  G06F17/00

CPC classification number: G01C21/20 ,  G01C21/005 ,  H03H17/0241 ,  H03H17/0285

Abstract: A vehicle navigation system uses a one-multiplier Gray-Markel filter. The sign parameter of each stage of the filter is selected by an algorithm which limits the maximum signal passing through the filter, thereby preventing overflow.

Abstract translation: 车载导航系统使用一个乘法器的Gray-Markel滤波器。 通过限制通过滤波器的最大信号的算法来选择滤波器各级的符号参数，从而防止溢出。

公开(公告)号：US4695970A

公开(公告)日：1987-09-22

申请号：US646869

申请日：1984-08-31

Applicant: Karl H. Renner ,  Alec J. Morton

Inventor： Karl H. Renner ,  Alec J. Morton

IPC: G06F17/10 ,  G10L19/06 ,  G10L19/14 ,  H03H17/02 ,  G06F15/31 ,  G10L1/00

CPC classification number: H03H17/0285 ,  G10L19/16 ,  G10L19/06

Abstract: An LPC digital lattice filter includes a full adder (44) which has one input thereof multiplexed with a multiplexer (46) and the other input thereof multiplexed by a multiplexer (50). Combination of the multiplication and addition steps with the full adder (44) results in the calculation of one of the digital filter equations. The result of each of these equations is either a Y-value or a B-value. The Y-values are stored in the output of a Y-register (78) and the B-values are stored in a nine stage B-stack (100) for delay thereof. The multiplexer (60) selects multiplicands from either the output of the one stage delay (86), from the B-stack (100) or the input excitation I. The multiplexer (46) selects addends from either the output of the B-stack (100), the output of the B-register (96) or from the multiplexers (60) or (66). The values are calculated in an interleaved sequence with a Y-value calculated and then a B-value calculated utilizing this generated Y-value. This generated Y-value is then used in calculating the next sequential Y-value and then discarded. However, the B-values are delayed until calculation of the next set of equations. The interleaved sequence allows use of only one set of delay stages.

Abstract translation: LPC数字网格滤波器包括全加器（44），其具有与多路复用器（46）复用的一个输入端，而另一输入端由多路复用器（50）复用。 乘法和加法步骤与全加器（44）的组合导致计算一个数字滤波器方程。 这些等式的每一个的结果是Y值或B值。 Y值存储在Y寄存器（78）的输出中，并且B值存储在九级B堆栈（100）中用于延迟。 多路复用器（60）从一级延迟（86）的输出，从B堆栈（100）或输入激励I中选择被乘数。多路复用器（46）从B堆栈的输出中选择加数 （100），B寄存器（96）的输出或多路复用器（60）或（66）的输出。 以计算的Y值的交错序列计算值，然后使用该生成的Y值计算B值。 然后将该生成的Y值用于计算下一个顺序Y值，然后丢弃。 然而，B值延迟到下一组方程的计算。 交错序列允许仅使用一组延迟级。

公开(公告)号：US4352162A

公开(公告)日：1982-09-28

申请号：US162614

申请日：1980-06-24

Applicant: Tomoaki Nyuji ,  Itaru Kawasaki ,  Masahiro Noguchi ,  Masahide Tsukamoto

Inventor： Tomoaki Nyuji ,  Itaru Kawasaki ,  Masahiro Noguchi ,  Masahide Tsukamoto

IPC: G10L13/047 ,  G10L19/06 ,  H03H17/02 ,  G06F15/34 ,  G10L1/00

CPC classification number: H03H17/0285 ,  G10L13/047 ,  G10L19/06

Abstract: A digital filter for a voice synthesis circuit which operates on the basis of the principle of linear predictive coding. More particularly, a digital filter of the lattice type for voice synthesis on the basis of the principle of linear predictive coding and capable of operating with a low clock frequency. Furthermore, the digital filter may use one multiplication circuit and one addition/subtraction circuit as well as containing an attenuation term element.

Abstract translation: 一种用于语音合成电路的数字滤波器，其基于线性预测编码的原理进行操作。 更具体地，基于线性预测编码的原理并且能够以低时钟频率操作的用于语音合成的格子类型的数字滤波器。 此外，数字滤波器可以使用一个乘法电路和一个加法/减法电路以及包含衰减项元件。

公开(公告)号：US09112479B2

公开(公告)日：2015-08-18

申请号：US13265288

申请日：2010-12-04

Applicant: Satya Sudhakar Yedlapalli ,  Kuchibhotla Venkata Subrahmanya Hari

Inventor： Satya Sudhakar Yedlapalli ,  Kuchibhotla Venkata Subrahmanya Hari

IPC: G06F17/10 ,  H03H17/02

CPC classification number: H03H17/025 ,  G01S1/76 ,  G01S3/805 ,  H03H17/0285 ,  H03H2017/0298 ,  H03H2218/04

Abstract: Various techniques are generally described for digital signal processing (DSP) such as discrete time filters. In some examples, a Canonic Filter Module (CFM) can be used to configure the discrete time filter using an LSF-Model with a finite length sequence. A single CFM can be configured to provide any type of discrete time filter used in signal processing. Filters can be modeled as a set of interconnected notch filters, a lattice structure of a discrete time filter is generally described that is based on a LSF-Model.

Abstract translation: 通常描述用于诸如离散时间滤波器的数字信号处理（DSP）的各种技术。 在一些示例中，可以使用Canonic Filter Module（CFM）来配置具有有限长度序列的LSF-Model的离散时间过滤器。 单个CFM可以配置为提供用于信号处理的任何类型的离散时间滤波器。 滤波器可以被建模为一组互连的陷波滤波器，通常描述基于LSF模型的离散时间滤波器的格子结构。

公开(公告)号：US4700323A

公开(公告)日：1987-10-13

申请号：US646868

申请日：1984-08-31

Applicant: Karl H. Renner ,  Alec J. Morton

Inventor： Karl H. Renner ,  Alec J. Morton

IPC: G06F7/544 ,  H03H17/02 ,  G06F15/31 ,  G10L1/00

CPC classification number: H03H17/0285 ,  G06F7/5443 ,  H03H17/02

Abstract: A system for processing a plurality of Equations includes a single full adder (44) which has the A input thereof multiplexed by multiplexer (62) and the B input thereof multiplexed by a multiplexer (94) and a multiplexer (66). The multiplexer (94) is operable to select a multiplicand for multiplication operations from a delay stack (54) for multiplication operations. The multiplication operation is performed by adding together partial products recording to Booth's modified algorithm. The partial products are generated by recode logic circuit (90) and (98). The recode logic circuits (90) and (98) are controlled by the multiplexed output from the multiplexer (80) which selects bits of a given multiplier stored in a K-stack (72). The multiplexer (62) in conjunction with the recode logic circuits (90) and (98) control reconfiguration of the adder (44) as a multiplication circuit. The addition operation is performed on the generated product by circulating the product back to the B-input of the adder (44) through the multiplexer (66). Data is selected from the output of a data stack (52) or from a D-register (108) which contains a prestored output value.

Abstract translation: 一种用于处理多个等式的系统包括一个单个全加器（44），其具有由多路复用器（62）复用的A输入端，并且由多路复用器（94）和多路复用器（66）复用的B输入端。 复用器（94）可操作以从用于乘法运算的延迟堆栈（54）中选择用于乘法运算的被乘数。 通过将部分产品记录添加到Booth的修改算法中来执行乘法运算。 部分产品由重新编码逻辑电路（90）和（98）产生。 重新编码逻辑电路（90）和（98）由多路复用器（80）的复用输出控制，该复用器选择存储在K堆栈（72）中的给定乘法器的位。 多路复用器（62）结合重新编码逻辑电路（90）和（98）控制加法器（44）的重配置作为乘法电路。 通过多路复用器（66）将产品循环回加法器（44）的B输入端，对产生的乘积进行加法运算。 从数据堆栈（52）的输出或包含预存储的输出值的D寄存器（108）中选择数据。