公开(公告)号：US20040259374A1

公开(公告)日：2004-12-23

申请号：US10867789

申请日：2004-06-16

申请人： NEC Electronics Corporation

发明人： Makoto Yasuda

IPC分类号： H01L021/4763

CPC分类号： H01L21/76814 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76865

摘要： The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted before applying the photo resist to reduce positive electric charge (step 12), and nitrogen plasma processing is conducted during the etching of the via hole and after the plasma stripping processing to reduce positive electric charge (steps 13 and 14), and the resistivity of the rinse liquid at the organic stripping is controlled to obtain equal to or lower than 0.3Mnull cm (step 15). Further, the RF-spattered thickness during the RF sputtering process for the barrier metal film is set to 18 nm to 22 nm to remove TiOn film (step 16).

摘要翻译： 选择用于形成Ti膜的溅射工艺的温度在200℃至225℃的温度范围内，以提供抵抗氧化的稳定的膜质量（步骤11）。 在施加光致抗蚀剂以减少正电荷之前进行紫外线照射（步骤12），并且在蚀刻过孔期间和等离子体剥离处理之后进行氮等离子体处理以减少正电荷（步骤13和14 ），并且将有机剥离时的冲洗液的电阻率控制为等于或低于0.3MOmega cm（步骤15）。 此外，将用于阻挡金属膜的RF溅射工艺期间的RF溅射厚度设定为18nm至22nm以除去TiO n膜（步骤16）。

公开(公告)号：US20040252804A1

公开(公告)日：2004-12-16

申请号：US10861355

申请日：2004-06-07

申请人： NEC Electronics Corporation

发明人： Morishige Aoyama

IPC分类号： H03D003/18

CPC分类号： H03D13/004 ,  H03L7/0814 ,  H03L7/093 ,  H03L7/107 ,  H04L7/0025 ,  H04L7/0337

摘要： A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1/DOWN1 signal, first and second integrators for integrating the UP1/DOWN1 signal and outputting an UP2/DOWN2 signal and an UP3/DOWN3 signal, respectively, a pattern generator for receiving the UP3/DOWN3 signal from the second integrator to output an UP4/DOWN4 signal, a mixer for receiving the UP2/DOWN2 signal from the first integrator and the UP4/DOWN4 signal from the pattern generator and generating an UP5/DOWN5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP5/DOWN5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.

摘要翻译： 用于跟踪调频输入数据的时钟和数据恢复电路包括用于接收数据信号和同步时钟信号的相位检测器，检测相位延迟或相位超前，并输出UP1 / DOWN1信号，第一和第二 用于积分UP1 / DOWN1信号并输出​​UP2 / DOWN2信号和UP3 / DOWN3信号的积分器，分别用于从第二积分器接收UP3 / DOWN3信号以输出UP4 / DOWN4信号的模式发生器，用于接收的混频器 来自第一积分器的UP2 / DOWN2信号和来自模式发生器的UP4 / DOWN4信号，并产生用于输出的UP5 / DOWN5信号;以及相位插值器，用于根据来自第二积分器的UP5 / DOWN5信号内插输入时钟信号的相位 提供用于输出的混频器。 从内插器输出的时钟信号作为时钟反馈到相位检测器。

公开(公告)号：US20040240288A1

公开(公告)日：2004-12-02

申请号：US10849906

申请日：2004-05-21

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi

IPC分类号： G11C007/00

CPC分类号： G11C11/40615 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C7/1066 ,  G11C11/406 ,  G11C2207/107 ,  G11C2207/2245

摘要： A semiconductor memory device that does not delay read/write access due to a refresh and can be interface compatible with a high-speed SRAM such as a QDR SRAM, comprises a plurality of subarrays each having a plurality of dynamic memory cells; at least one cache memory for the plurality of subarrays; a circuit to check whether data read from the subarray selected by a read address is present in the cache memory or not; and a circuit performing control so that the check result indicates that the data is present in the cache memory, the data is read from the cache memory and refreshing of the subarray is performed concurrently with a read cycle.

摘要翻译： 一种半导体存储器件，其不会由于刷新而延迟读/写访问，并且可以与诸如QDR SRAM的高速SRAM接口兼容，包括多个子阵列，每个子阵列具有多个动态存储器单元; 用于所述多个子阵列的至少一个高速缓冲存储器; 用于检查从读取地址选择的子阵列读取的数据是否存在于高速缓冲存储器中的电路; 执行控制使得检查结果指示数据存在于高速缓冲存储器中的电路，从高速缓冲存储器读取数据，并且以读周期同时执行子阵列的刷新。

公开(公告)号：US20040239374A1

公开(公告)日：2004-12-02

申请号：US10846674

申请日：2004-05-17

申请人： NEC Electronics Corporation

发明人： Yoshihiko Hori

IPC分类号： H03K005/22

CPC分类号： H04L5/20 ,  H03K5/003 ,  H04L25/0272 ,  H04L25/0278

摘要： The intermediate node of the first terminator connected between a pair of signal lines transmitting the first differential signal with one side of the third differential signal as a common voltage and the intermediate node of the second terminator connected between a pair of signal lines transmitting the second differential signal with the other side of the third differential signal as a common voltage are connected by the intermediate connection. Thus, the intermediate node of the first terminator and the intermediate node of the second terminator act as a virtual ground of the third differential signal, enabling the matching of the impedance of the terminators related to the third differential signal and the impedance of the signal lines related to the third differential signal. It is thus able to prevent the reflection of the third differential signal.

摘要翻译： 连接在一对信号线之间的第一终端器的中间节点连接在一对信号线之间，该信号线将第三差分信号的一侧作为公共电压发送，第二终端器的中间节点连接在发送第二差分信号的一对信号线之间 第三差分信号的另一侧的信号作为公共电压通过中间连接连接。 因此，第一终端器的中间节点和第二终端器的中间节点用作第三差分信号的虚拟接地，使得能够匹配与第三差分信号相关的终端器的阻抗和信号线的阻抗 与第三差分信号有关。 因此能够防止第三差分信号的反射。

公开(公告)号：US20040238964A1

公开(公告)日：2004-12-02

申请号：US10855562

申请日：2004-05-28

申请人： NEC ELECTRONICS CORPORATION

发明人： Masaya Kawano ,  Yoshiaki Yamamoto ,  Takamasa Ito

IPC分类号： H01L021/4763

CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.

摘要翻译： 本发明的半导体器件包括第一互连，连接到第一互连的通孔，以及与通孔连接形成为单个单元的第二互连。 通孔塞的横截面形状使得指示通孔塞侧壁相对于第一互连件的表面的角度的插塞侧壁角度为正角度; 此外，在插塞侧壁角达到最大值的过孔塞的横截面形状的两个侧壁的至少一个侧壁上，在通孔塞的基部和顶部之间至少存在两个点。 由于在通孔塞侧壁中不会形成会产生应力集中的形状，所以金属更有效地嵌入到通路孔中，能够防止空隙的发生。

公开(公告)号：US20040238894A1

公开(公告)日：2004-12-02

申请号：US10856999

申请日：2004-06-01

申请人： NEC Electronics Corporation

发明人： Hiroshi Furuta

IPC分类号： H01L023/62

CPC分类号： H01L27/0266 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

摘要： A protection element comprises a ring-shape gate electrode, an Nnull drain region inside the ring-shape gate electrode, an Nnull source region outside, and a shield plate electrode. The ring gate and source regions are connected to ground via a through-hole, and the drain region is connected to an external pad. The shield plate electrode is connected to ground or to a power supply. Element isolation is achieved by the shield plate electrode, without forming a LOCOS or other element isolation oxide layer. By this means, blocking of thermal conduction by an oxide layer can be avoided to improve the heat dissipation and ESD resistance of the protection element.

摘要翻译： 保护元件包括环形栅电极，环形栅电极内的N +漏极区域，外侧的N +源极区域和屏蔽板电极。 环形栅极和源极区域经由通孔连接到地，并且漏极区域连接到外部焊盘。 屏蔽板电极连接到地或电源。 通过屏蔽板电极实现元件隔离，而不形成LOCOS或其它元件隔离氧化物层。 通过这种方式，可以避免阻挡氧化层的热传导，从而改善保护元件的散热和耐ESD性。

公开(公告)号：US20040232445A1

公开(公告)日：2004-11-25

申请号：US10849835

申请日：2004-05-21

申请人： NEC Electronics Corporation

发明人： Norihito Nakamoto

IPC分类号： H01L027/10

CPC分类号： G06F17/5068 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is provided in an interconnect layer different from the interconnect layer of the first conductor and which intersects the first conductor by solid crossing, is not less than the line width of the first conductor, and if, in case the center point of the via is arranged on a center axis along the longitudinal direction of the first conductor, the minimum spacing cannot be maintained between the first conductor and the line neighboring to the first conductor, the center of the via, arranged on the first conductor, is placed with an offset of a predetermined value with respect to the longitudinal center axis of the first conductor, so that a spacing not less than the minimum spacing is maintained between the first conductor and the line neighboring to the first conductor and in the via placement region on the first conductor.

摘要翻译： 一种半导体器件，布局器件和布局方法，其中，如果将互连层中提供的第一导体和设置在不同于第一导体的互连层的互连层中的第二导体互连的通孔的尺寸和 与第一导体相交的第一导体与第一导体的线宽不小于第一导体的线宽，并且如果在通孔的中心点沿着第一导体的纵向方向布置在中心轴上的情况下，最小间隔 不能保持在第一导体和与第一导体相邻的线之间，布置在第一导体上的通孔的中心相对于第一导体的纵向中心轴线以预定值的偏移量放置，因此 在第一导体和与第一导体相邻的线之间以及在通孔放置区域o中保持不小于最小间隔的间隔 在第一个指挥。

公开(公告)号：US20040227573A1

公开(公告)日：2004-11-18

申请号：US10838221

申请日：2004-05-05

申请人： NEC Electronics Corporation

发明人： Masaaki Soda

IPC分类号： H03F003/45 ,  H03H011/00

CPC分类号： H03F3/45381 ,  H03F1/483 ,  H03F3/45394 ,  H03F2203/45488 ,  H03F2203/45631 ,  H03F2203/45632 ,  H03F2203/45641 ,  H03F2203/45648 ,  H03H11/48

摘要： An active inductance circuit comprising a signal terminal (OUT) and having voltage and current characteristics, as viewed from this terminal, which are identical to those of a circuit comprising an inductance, this active inductance circuit having a structure in which the drain terminal of a first MOS transistor M1 and the gate terminal of a second MOS transistor M2 different in conductivity type from the first MOS transistor are connected to the signal terminal, the gate terminal of the first MOS transistor is connected to the source terminal of the second MOS transistor, a capacitor and a current source are connected to the source terminal of the second transistor, the source terminal of the first MOS transistor and the drain terminal of the second MOS transistor are connected to a power source and other terminals of the capacitor and current source are connected to another power source.

摘要翻译： 一种有源电感电路，包括信号端子（OUT），并具有从该端子观察的电压和电流特性，其与包括电感的电路相同，该有源电感电路具有这样的结构，其中， 第一MOS晶体管M1和与第一MOS晶体管不同的导电类型的第二MOS晶体管M2的栅极端子连接到信号端子，第一MOS晶体管的栅极端子连接到第二MOS晶体管的源极端子， 电容器和电流源连接到第二晶体管的源极端子，第一MOS晶体管的源极端子和第二MOS晶体管的漏极端子连接到电源，电容器和电流源的其它端子 连接到另一个电源。

公开(公告)号：US20040207441A1

公开(公告)日：2004-10-21

申请号：US10844545

申请日：2004-05-13

申请人： NEC Electronics Corporation

发明人： Takanori Saeki

IPC分类号： G06F001/04

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/133 ,  H03K5/14 ,  H04L7/0337

摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

公开(公告)号：US20040207434A1

公开(公告)日：2004-10-21

申请号：US10824596

申请日：2004-04-15

申请人： NEC Electronics Corporation

发明人： Makoto Miura

IPC分类号： H03D013/00

CPC分类号： G09G3/3688 ,  G09G2330/021 ,  H03F3/3023 ,  H03F3/45237 ,  H03F2203/30021 ,  H03F2203/45726

摘要： In a driver, a voltage-follower-type operational amplifier receives current input data to generate an output signal. A transient state detecting circuit detects a transient state in the current input data to generate a first pulse signal when the current input data is increased and generate a second pulse signal when the current input data is decreased. A switch circuit substantially increases corresponding load currents flowing through the voltage-follower-type operational amplifier in accordance with the first and second pulse signals.

摘要翻译： 在驱动器中，电压跟随器型运算放大器接收当前输入数据以产生输出信号。 瞬态状态检测电路在当前输入数据增加时检测当前输入数据中的过渡状态，以产生第一脉冲信号，并且当当前输入数据减小时产生第二脉冲信号。 开关电路根据第一和第二脉冲信号基本上增加流过电压跟随器型运算放大器的对应负载电流。