公开(公告)号：US06598105B1

公开(公告)日：2003-07-22

申请号：US09290853

申请日：1999-04-13

申请人： Jacob K. Oshins ,  Andrew J. Thornton

发明人： Jacob K. Oshins ,  Andrew J. Thornton

IPC分类号： G06F1326

CPC分类号： G06F13/24 ,  G06F9/4411

摘要： An interrupt arbiter for a computer is described. The arbiter allocates interrupt resources to a plurality of devices within a computer such as a modem, keyboard, video controller, serial port, PCMCIA card, etc. As devices request interrupt resources, the inventive arbiter uses the Advanced Configuration and Power Interface (ACPI) to allocate interrupt resources based on the actual hardware topology of the computer. The improved arbiter allocates the interrupt resources by using configuration information that conforms to the ACPI specification and that describes the underlying connection circuitry, such as the multiplexors, routers, switches, etc., that communicates interrupt signals generated by the devices. In addition, the arbiter reconfigures connection circuitry of the computing system when necessary in order to improve the allocation of interrupt resources.

摘要翻译： 描述了计算机的中断仲裁器。 仲裁器将中断资源分配给诸如调制解调器，键盘，视频控制器，串行端口，PCMCIA卡等的计算机内的多个设备。当设备请求中断资源时，本发明的仲裁器使用高级配置和电源接口（ACPI） 根据计算机的实际硬件拓扑分配中断资源。 改进的仲裁器通过使用符合ACPI规范的配置信息来分配中断资源，并描述了传递由设备生成的中断信号的多路复用器，路由器，交换机等底层连接电路。 另外，为了改善中断资源的分配，仲裁器在必要时重新配置计算系统的连接电路。

公开(公告)号：US06772260B2

公开(公告)日：2004-08-03

申请号：US09847448

申请日：2001-05-02

申请人： Yuji Kawase ,  Satoru Imai

发明人： Yuji Kawase ,  Satoru Imai

IPC分类号： G06F1326

CPC分类号： G06F13/26

摘要： An interrupt signal generating device comprises interrupt detection units (20) each adapted to output a detection signal (DET-1 to DET-n) in response to a respective input signal (IN-1 to IN-n) representing an interrupt event; and an interrupt handler unit (15). The interrupt handler has a plurality of input terminals for receiving the detection signals (DET-1 to DET-n) and a plurality of output terminals for outputting corresponding interrupt signals to a CPU, and signal distribution means (16) connecting said input terminals to said output terminals and establishing a predetermined but changeable assignment between the input and output terminals, wherein each of said input terminals is assigned to one of said outputs terminals such that an interrupt signal (INT-1 to INT-n) is output from this output terminal in response to a detection signal (DET-1 to DET-n) applied to the respective input terminal.

摘要翻译： 中断信号产生装置包括中断检测单元（20），每个中断检测单元适于响应于表示中断事件的相应输入信号（IN-1至IN-n）输出检测信号（DET-1至DET-n） 和中断处理单元（15）。 中断处理器具有用于接收检测信号（DET-1至DET-n）的多个输入端子和用于向CPU输出相应的中断信号的多个输出端子;以及信号分配装置（16），将所述输入端子连接到 所述输出端并在所述输入和输出端之间建立预定但可变化的分配，其中每个所述输入端分配给所述输出端中的一个，使得从该输出输出中断信号（INT-1至INT-n） 响应于施加到相应输入端子的检测信号（DET-1至DET-n）。

公开(公告)号：US06681281B1

公开(公告)日：2004-01-20

申请号：US09715606

申请日：2000-11-17

申请人： Timothy C. Maleck

发明人： Timothy C. Maleck

IPC分类号： G06F1326

CPC分类号： G06F13/26

摘要： A system and method for implementing a multi-level interrupt scheme in a computer system is provided. Bus devices and a bus controller may be coupled to a shared bus in a computer system. The bus may include an interrupt line for each bus device coupled to the bus. A bus device may be configured to convey an interrupt using its designated interrupt line. Each bus device may be configured to convey different types of interrupt signals on its interrupt line depending on an interrupt priority level of a given interrupt. The bus controller may be configured to receive interrupt signals from each bus device coupled to the bus and may arbitrate amongst the interrupt signals based on the interrupt priority level of each interrupt signal. The bus controller may grant the interrupt that corresponds to the highest priority level. If multiple interrupts correspond to the same highest priority level in a group of interrupts, then the bus controller may use any suitable arbitration scheme to grant an interrupt.

摘要翻译： 提供了一种用于在计算机系统中实现多级中断方案的系统和方法。 总线装置和总线控制器可以耦合到计算机系统中的共享总线。 总线可以包括用于耦合到总线的每个总线设备的中断线。 总线设备可以被配置为使用其指定的中断线传送中断。 每个总线设备可以被配置为根据给定中断的中断优先级来在其中断线上传送不同类型的中断信号。 总线控制器可以被配置为从耦合到总线的每个总线设备接收中断信号，并且可以基于每个中断信号的中断优先级来仲裁中断信号。 总线控制器可以授予与最高优先级相对应的中断。 如果多个中断对应于一组中断中相同的最高优先级，则总线控制器可以使用任何合适的仲裁方案来授予中断。

公开(公告)号：US06397282B1

公开(公告)日：2002-05-28

申请号：US09287485

申请日：1999-04-06

申请人： Hiroshi Hashimoto ,  Kazuya Iwamoto ,  Yuji Nagatani

发明人： Hiroshi Hashimoto ,  Kazuya Iwamoto ,  Yuji Nagatani

IPC分类号： G06F1326

CPC分类号： H04L29/06027 ,  H04L29/06

摘要： A communication controller comprises a storage for storing data of a message being received, a determining unit for determining types of the message being received, and a transmission controller for generating interrupt requests for transferring data to a data processing unit at a different timing responsive to determination by the determining unit. That is, if the message being received requires immediate processing, the transmission controller immediately transmits an interrupt request signal to a CPU. The CPU then reads from the storage not only the data which require urgent processing but also all the data stored in the storage, and stores the data in its memory. If the message does not require immediate processing, the transmission controller transmits the interrupt request signal to the CPU when the data stored in the storage have reached a predetermined amount or when a predetermined time has elapsed from a time that the data began to be stored in the storage.

摘要翻译： 通信控制器包括：存储器，用于存储正在接收的消息的数据;确定单元，用于确定正在接收的消息的类型;以及传输控制器，用于产生用于响应于确定的不同定时向数据处理单元传送数据的中断请求 由确定单元。 也就是说，如果接收到的消息需要立即处理，则传输控制器立即向CPU发送中断请求信号。 CPU然后从存储器读取不仅需要紧急处理的数据，而且读取存储在存储器中的所有数据，并将数据存储在其存储器中。 如果消息不需要立即处理，则当存储在存储器中的数据已经达到预定量时或者当从数据开始存储的时间起经过了预定时间时，传输控制器将中断请求信号发送到CPU 存储。

公开(公告)号：US06502152B1

公开(公告)日：2002-12-31

申请号：US09410743

申请日：1999-10-01

申请人： Gilbert Laurenti

发明人： Gilbert Laurenti

IPC分类号： G06F1326

CPC分类号： G06F9/3879 ,  G06F9/32

摘要： A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. Two sets of interrupt vectors are maintained. Interrupts vectors pertaining to interrupts originated by one set of interrupt sources (820, 821, 822) are stored in a DSP interrupt vector table (850) located in a memory circuit 801 that is private to the DSP. Interrupt vectors pertaining to interrupts originated by a host processor (810) are stored in a Host interrupt vector table (851) located in a dual ported communication memory circuit (802). The DSP executes interrupt service routines to service all of the interrupts, but the host can change the interrupt vectors for host initiated interrupts.

摘要翻译： 提供了具有可变指令长度的可编程数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。 架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。 保持两组中断向量。 由一组中断源（820,821,822）产生的与中断有关的中断向量存储在位于DSP专用的存储器电路801中的DSP中断向量表（850）中。 与由主处理器（810）发起的中断相关的中断向量存储在位于双端口通信存储电路（802）中的主机中断向量表（851）中。 DSP执行中断服务程序以服务所有中断，但主机可以更改主机发起中断的中断向量。

公开(公告)号：US06430643B1

公开(公告)日：2002-08-06

申请号：US09389438

申请日：1999-09-02

申请人： Richard Louis Arndt

发明人： Richard Louis Arndt

IPC分类号： G06F1326

CPC分类号： G06F13/26 ,  G06F2213/2412 ,  G06F2213/2418

摘要： An interrupt handling mechanism within a data processing system is used to assign interrupts among multiple interrupt presentation controllers while avoiding the use of a significant amount of signal lines. An interrupt input message from an interrupt source controller is input into an interrupt presentation controller. Fields are added to the interrupt input message to facilitate the assignment of the interrupt input message to an interrupt presentation controller. The input interrupt message is passed between the interrupt presentation controller in a sequential fashion such that the collection of controllers forms a logical ring. On the first circle of the ring, the priority of the processors capable of handling the interrupt is discovered. A second pass through the interrupt presentation controller is used to assign the first processor that is both capable of taking the interrupt and also has an equal or lower priority to that noted on the first pass as to best priority. The condition in which no acceptable processors are found for servicing the interrupt request is provided for by rejecting the interrupt.

摘要翻译： 数据处理系统中的中断处理机制用于在多个中断呈现控制器之间分配中断，同时避免使用大量的信号线。 来自中断源控制器的中断输入消息被输入到中断呈现控制器中。 字段被添加到中断输入消息，以便于将中断输入消息分配给中断呈现控制器。 输入中断消息以顺序方式在中断呈现控制器之间传递，使得控制器的集合形成逻辑环。 在环的第一圈，发现能处理中断的处理器的优先级。 通过中断呈现控制器的第二次通过用于分配能够进行中断的第一处理器，并且具有与第一次通过中所指出的优先级相同或更低的优先级。 通过拒绝中断来提供不能接受处理器用于维护中断请求的条件。

公开(公告)号：US06269419B1

公开(公告)日：2001-07-31

申请号：US09243781

申请日：1999-02-03

申请人： Hideki Matsuyama

发明人： Hideki Matsuyama

IPC分类号： G06F1326

CPC分类号： G06F9/4818

摘要： In an information processing apparatus, an interrupt control apparatus and method controls interrupt request inputs with respect to a processor. The interrupt control apparatus includes an interrupt flag holding circuit for holding a plurality of flags indicative of interrupt factors with respect to the respective interrupt request inputs and also holds a plurality of interrupt levels representative of priority orders of the interrupt request inputs. An interrupt level judging circuit judges an interrupt level having a top priority and also outputs an interrupt request to the processor. An interrupt vector generating circuit generates an interrupt vector in response to the held interrupt factor and an interrupt vector outputting circuit outputs the held interrupt vector to the processor. The processing operations by all of these circuits are carried out in a pipeline processing manner so that when an interrupt request having a higher interrupt level than that of an interrupt request under execution is issued, the processor interrupts the interrupt process operation under execution and executes an interrupt process operation for the higher interrupt level. When the interrupt process operation for the higher interrupt level is accomplished, the processor clears the interrupt level held in the interrupt level judging circuit and restarts the interrupt process operation for the lower interrupt level.

摘要翻译： 在信息处理装置中，中断控制装置和方法控制关于处理器的中断请求输入。 该中断控制装置包括一个中断标志保持电路，用于保存指示相应中断请求输入的中断因素的多个标志，并且还保存代表中断请求输入的优先顺序的多个中断电平。 中断电平判断电路判断具有最高优先级的中断电平，并且还向处理器输出中断请求。 中断向量产生电路响应于保持的中断因子产生中断向量，并且中断向量输出电路将保持的中断向量输出到处理器。 所有这些电路的处理操作以流水线处理的方式进行，以便当发出具有比执行中的中断请求更高的中断级别的中断请求时，处理器中断执行中的中断处理操作并执行 中断处理操作为较高的中断级别。 当中断处理操作为较高的中断级别完成时，处理器将清除中断级别判断电路中保持的中断级别，并重新启动中断处理操作以降低中断级别。

公开(公告)号：US06253263B1

公开(公告)日：2001-06-26

申请号：US09176534

申请日：1998-10-21

申请人： Marco Losi ,  Sergio Pelagalli

发明人： Marco Losi ,  Sergio Pelagalli

IPC分类号： G06F1326

CPC分类号： G06F13/24

摘要： A peripheral device connecting system with priority arbitration includes a connection matrix connected to a plurality of peripheral devices capable of transmitting a signal to be arbitrated, e.g., an interrupt enable signal. The connection matrix includes first and second connection matrices connected to each other through a plurality of logic gates having a progressive number of inputs for transmitting in parallel a plurality of signals to be arbitrated. A connection matrix for a microcontroller-emulating chip includes a peripheral device connecting system with priority arbitration.

摘要翻译： 具有优先仲裁的外围设备连接系统包括连接到能够发送要被仲裁的信号的多个外围设备的连接矩阵，例如中断使能信号。 连接矩阵包括通过具有渐进数量的输入的多个逻辑门相互连接的第一和第二连接矩阵，用于并行传输要被仲裁的多个信号。 用于微控制器仿真芯片的连接矩阵包括具有优先仲裁的外围设备连接系统。

公开(公告)号：US06764017B2

公开(公告)日：2004-07-20

申请号：US10151926

申请日：2002-05-22

申请人： Jui-Chung Chen ,  Po-Jen Hsueh ,  Sidney Young ,  Ping-Chang Liu

发明人： Jui-Chung Chen ,  Po-Jen Hsueh ,  Sidney Young ,  Ping-Chang Liu

IPC分类号： G06F1326

CPC分类号： G06K19/0719 ,  G06K19/07

摘要： A multi-function electronic card has a host interface, a multi-functional controller and a plurality of function devices. Each function device is connected to the host via the host interface by issuing an interrupt request to the multi-functional controller. The multi-functional controller has an interrupt queue and an interrupt status register, each bit of the interrupt status register corresponding to a function device. When a function device issues an interrupt request, an identification number of the function device is stored into the interrupt queue, and only when all the bits in the interrupt status register are zeros, a corresponding bit in the interrupt status register is set as 1 for issuing an interrupt request to the host. When the host has serviced the function device, the interrupt queue is updated and the interrupt status register is cleared.

摘要翻译： 多功能电子卡具有主机接口，多功能控制器和多个功能设备。 每个功能设备通过主机接口通过向多功能控制器发出中断请求而连接到主机。 多功能控制器具有中断队列和中断状态寄存器，中断状态寄存器的每个位与功能设备相对应。 当功能设备发出中断请求时，功能设备的标识号被存储到中断队列中，只有当中断状态寄存器中的所有位为零时，中断状态寄存器中的相应位才被设置为1 向主机发出中断请求。 当主机对功能设备进行维修时，更新中断队列，并清除中断状态寄存器。

公开(公告)号：US06633942B1

公开(公告)日：2003-10-14

申请号：US09408670

申请日：1999-09-30

申请人： Sivaram Balasubramanian

发明人： Sivaram Balasubramanian

IPC分类号： G06F1326

CPC分类号： G06F13/26 ,  G05B19/0423 ,  G05B2219/25416 ,  G05B2219/31218 ,  G05B2219/32266 ,  Y02P90/20

摘要： An interrupt handler is provided for a real-time control system that prevents interrupts which occur asynchronously with respect to control tasks from upsetting guarantees of timely execution of the control tasks. For interrupts associated with the communication of messages between portions of a control task over the distributed system, the interrupts are converted to proxy tasks that may be scheduled like any task in a multitasked-operated system. More generally, interrupts may be assigned to a predetermined interrupt window being a portion of the total processing bandwidth of the processor. In pre-allocating the processor bandwidth to the control tasks, this interrupt window may be subtracted out thereby guaranteeing adequate bandwidth for both interrupt processing and user tasks.

摘要翻译： 为实时控制系统提供一个中断处理程序，可以防止相对于控制任务异步发生的中断，从而破坏及时执行控制任务的保证。 对于与通过分布式系统的控制任务的部分之间的消息通信相关联的中断，将中断转换为可以像多任务操作的系统中的任何任务一样被调度的代理任务。 更一般地，可以将中断分配给作为处理器的总处理带宽的一部分的预定中断窗口。 在将处理器带宽预先分配给控制任务时，可以减去该中断窗口，从而为中断处理和用户任务保证足够的带宽。