公开(公告)号：US07864555B2

公开(公告)日：2011-01-04

申请号：US12200624

申请日：2008-08-28

申请人： Mayumi Inage ,  Akio Iwata ,  Gaku Ito

发明人： Mayumi Inage ,  Akio Iwata ,  Gaku Ito

IPC分类号： G11C5/02 ,  G11C4/00 ,  G11C5/14

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  Y10T29/49002

摘要： A pair of power supply lines that are orthogonal to the border with the cell array are placed, for each one-bit processing circuit of the data processing unit, in a semiconductor storage device such as SRAM or the like comprising a data processing unit for writing data to memory cells and reading it therefrom, a row decode unit for driving the word lines of the memory cells, and a timing control unit for generating a control pulse for the data processing unit, all of which are arranged around the circumference of a cell array in which memory cells are arrayed in a grid-like fashion. MOS transistors are placed between the power supply lines in such a position that the principal axis direction of the gate pattern is orthogonal to the two aforementioned wirings, and are closely arrayed in the longitudinal direction of the power supply lines.

摘要翻译： 对于数据处理单元的每个1位处理电路，将与单元阵列的边界正交的一对电源线放置在诸如SRAM等的半导体存储装置中，包括用于写入的数据处理单元 数据到存储器单元并从其读取，行解码单元，用于驱动存储单元的字线;以及定时控制单元，用于产生用于数据处理单元的控制脉冲，所述控制脉冲都围绕单元周围排列 存储单元以阵列方式排列的阵列。 将MOS晶体管放置在电源线之间，使得栅极图案的主轴方向与两条上述布线正交，并且在电源线的长度方向上紧密排列。