公开(公告)号：US08279698B2

公开(公告)日：2012-10-02

申请号：US13285445

申请日：2011-10-31

申请人： Joong-Ho Lee

发明人： Joong-Ho Lee

IPC分类号： G17C7/02

CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C7/1066 ,  G11C7/18 ,  G11C2207/005

摘要： A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

摘要翻译： 半导体存储器件包括被配置为形成存储单元矩阵并且分别包括第一位线和第二位线的第一和第二子存储器单元区域，以形成对应于预定存储器单元的数据传输路径，附加位线 被配置为跨越第一子存储单元区域并通过与第二位线连接形成数据传送路径;感测和放大单元，被配置为感测和放大通过附加位线和第一位线输入的数据。