公开(公告)号：US07531396B2

公开(公告)日：2009-05-12

申请号：US11374418

申请日：2006-03-14

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

IPC分类号： H01L21/338 ,  H01L21/066

CPC分类号： H01L29/66068 ,  H01L21/8213 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7828

摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.

摘要翻译： 公开了制造半导体器件的方法。 半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极 异质半导体区域和半导体本体通过栅极绝缘膜。 该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺 从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。