Gate line edge roughness reduction by using 2P/2E process together with high temperature bake
    1.
    发明授权
    Gate line edge roughness reduction by using 2P/2E process together with high temperature bake 有权
    通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低

    公开(公告)号:US08304317B2

    公开(公告)日:2012-11-06

    申请号:US12648802

    申请日:2009-12-29

    IPC分类号: H01L21/8324

    CPC分类号: H01L21/28123 H01L21/32139

    摘要: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

    摘要翻译: 图案化多个多晶硅结构的方法包括在半导体本体上形成多晶硅层,并使用减少线边缘粗糙度(LER)的第一图案化工艺来图案化多晶硅层以形成第一多晶硅结构。 该方法还包括使用在执行第一图案化工艺之后与第一图案化工艺不同的第二图案化工艺来图案化多晶硅层以形成第二多晶硅结构。