公开(公告)号：US06340911B1

公开(公告)日：2002-01-22

申请号：US08784775

申请日：1997-01-16

申请人： Hiroshi Kanno

发明人： Hiroshi Kanno

IPC分类号： H03K19017

CPC分类号： H03K19/017527

摘要： Disclosed herein is a level conversion circuit which operates at high speeds even at a low power-supply voltage. The level conversion circuit is largely constituted by an emitter follower section 101, an amplitude amplification section 102, and a level conversion section 103. The amplitude amplification section 102 is a differential amplifier constructed so that the gate of an N-channel MOS transistor M1 is connected to a node 001, the connection node 002 of the drain is connected to a high power-supply terminal VCC through a resistor R2, the source is connected to a node 004, the base of an N-channel MOS transistor M2 is connected to a reference power-supply terminal VR, the connection node 003 of the drain is connected to the high power-supply terminal VCC through a resistor R3, the source is connected to a node 004, the base of an NPN transistor Q4 is connected to a reference power-supply terminal VCSI, the collector is connected to the node 004, and the emitter is connected to the first low power-supply terminal GND1 through a resistor R4.

摘要翻译： 这里公开了即使在低电源电压下也以高速运行的电平转换电路。 电平转换电路主要由射极跟随部分101，幅度放大部分102和电平转换部分103构成。幅度放大部分102是构造成使N沟道MOS晶体管M1的栅极为 连接到节点001，漏极的连接节点002通过电阻器R2连接到高电源端子VCC，源极连接到节点004，N沟道MOS晶体管M2的基极连接到 参考电源端子VR，漏极的连接节点003通过电阻器R3连接到高电源端子VCC，源极连接到节点004，NPN晶体管Q4的基极连接到 参考电源端子VCSI，集电极连接到节点004，发射极通过电阻R4连接到第一低电源端子GND1。

公开(公告)号：US06366133B1

公开(公告)日：2002-04-02

申请号：US09498765

申请日：2000-02-04

申请人： William Bryan Barnes

发明人： William Bryan Barnes

IPC分类号： H03K19017

CPC分类号： G11C8/10 ,  G11C8/08

摘要： A wordline driver has enable circuitry optimized for positive-going input transitions and disable circuitry optimized for transitions in a disable input which would cause the output to become disabled. The optimization is achieved by suitably dimensioning the transistors in the respective enable and disable circuits for suitable current-carrying ability.

摘要翻译： 字线驱动器具有针对正向输入转换优化的使能电路，并禁用针对禁用输入中的转换进行优化的电路，这将导致输出变为禁止。 通过在相应的使能和禁用电路中适当地确定晶体管的尺寸来实现优化，以获得合适的载流能力。

公开(公告)号：US06492836B2

公开(公告)日：2002-12-10

申请号：US09726984

申请日：2000-11-30

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： H03K19017

CPC分类号： H03K5/1252 ,  H03K3/3565 ,  H03K5/159 ,  H03K17/167

摘要： A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring a rising edge or a falling edge in accordance with a control signal. The second stage also includes a feedback loop coupled to an output of the second stage. The feedback loop provides the control signal for switching the switching circuit to favor the rising edge or falling edge.