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公开(公告)号：US06617874B2
公开(公告)日：2003-09-09
申请号：US10038196
申请日：2002-01-02
申请人： Lawrence S. Uzelac
发明人： Lawrence S. Uzelac
IPC分类号： H03K19173
CPC分类号： H03K3/356008 , H03K17/223 , H03K2217/0036
摘要： A power-up reference circuit and related method that generates a reference voltage in response to the circuit being powered up. The circuit includes a power-up sensing circuit that generates a set signal, a latch to generate and sustain the reference voltage in response to the set signal, and a reset key decoder to receive an N-bit key and in response thereto generate a reset signal that causes the latch to reset. Upon the circuit being powered up, the power-up sensing circuit generates the set signal which sets the latch to generate the reference voltage. The reference voltage can be used by other circuits to initialize their operating conditions. Once the reference voltage has been used, the N-bit key is generated which causes the decoder to generate the reset signal, which in turn, causes the latch to reset. When the latch is reset, the power-up reference circuit consumes substantially no power.
摘要翻译： 上电参考电路和相关方法，其响应于电路被加电产生参考电压。 该电路包括产生设置信号的上电感测电路，响应于设定信号产生和维持参考电压的锁存器，以及用于接收N位密钥的复位密钥解码器，并且响应于此产生复位 信号使锁存器复位。 在电路通电时，上电感测电路产生设置锁存器以产生参考电压的置位信号。 其他电路可以使用参考电压来初始化其工作条件。 一旦使用了参考电压，就产生N位键，使得解码器产生复位信号，这又导致锁存器复位。 当锁存器复位时，上电参考电路基本上不消耗电能。
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2.发明授权Method and apparatus for reducing sub-threshold off current for a real time clock circuit during battery operation 失效用于在电池操作期间减少实时时钟电路的次阈值关断电流的方法和装置公开(公告)号：US06957354B2
公开(公告)日：2005-10-18
申请号：US10625584
申请日：2003-07-22
申请人： Lawrence S. Uzelac , Andrew M. Volk
发明人： Lawrence S. Uzelac , Andrew M. Volk
摘要： A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.
摘要翻译： 用于低泄漏电池操作的CMOS电路在电源不可用时将实时时钟连接到可用时的电源或低泄漏源。
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公开(公告)号：US06650170B1
公开(公告)日：2003-11-18
申请号：US10259080
申请日：2002-09-27
申请人： Lawrence S. Uzelac
发明人： Lawrence S. Uzelac
IPC分类号： H01L3500
CPC分类号： H01L27/0629
摘要： According to some embodiments, a drive circuit provides an output resistance substantially stable despite variations in operating temperature.
摘要翻译： 根据一些实施例，尽管工作温度有变化，驱动电路提供了基本稳定的输出电阻。
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4.发明授权Method and apparatus for changing bias levels to reduce CMOS leakage of a real time clock when switching to a battery mode of operation 失效用于在切换到电池操作模式时改变偏置电平以减少实时时钟的CMOS泄漏的方法和装置公开(公告)号：US06611918B1
公开(公告)日：2003-08-26
申请号：US09469986
申请日：1999-12-21
申请人： Lawrence S. Uzelac
发明人： Lawrence S. Uzelac
IPC分类号： G06F132
摘要： A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.
摘要翻译： 用于低泄漏电池操作的CMOS电路在电源不可用时将实时时钟连接到可用时的电源或低泄漏源。
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5.发明授权公开(公告)号：US07406609B2
公开(公告)日：2008-07-29
申请号：US11221694
申请日：2005-09-08
申请人： Lawrence S. Uzelac , Andrew M. Volk
发明人： Lawrence S. Uzelac , Andrew M. Volk
摘要： Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.
摘要翻译： 使用本系统和技术可以最小化半导体逻辑中的泄漏电流。 例如，当电源不可用时，用于低泄漏电池操作的CMOS电路可以将实时时钟连接到电源，或者在可用时连接到低电压源。
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6.发明授权Circuit in which the time delay of an input clock signal is dependent only on its logic phase width and a ratio of capacitances 失效其中输入时钟信号的时间延迟仅取决于其逻辑相位宽度和电容比的电路公开(公告)号：US06834355B2
公开(公告)日：2004-12-21
申请号：US09738695
申请日：2000-12-15
申请人： Lawrence S. Uzelac
发明人： Lawrence S. Uzelac
IPC分类号： G06F104
摘要： The invention provides, in an embodiment, a structure, method and means for generating clock phases, synchronized to the system clock, that to first order are independent of process parameters including drive current, parasitic resistance and parasitic capacitance. In one aspect, an apparatus is provided to generate an output phase at a predetermined time relative to an input clock signal and dependent on a logic phase width of the input clock signal. In another aspect, the apparatus includes similar circuit components with unequal units, the predetermined time is further dependent on the units ratio of the similar circuit components. In another aspect, the apparatus is cascaded with at least one reproduction of the apparatus, and configured to provide a multiple of the input clock signal. In another aspect, the apparatus is coupled in parallel with at least one reproduction of the apparatus, and configured to provide at least two output phases generated in parallel during the input clock signal.
摘要翻译： 本发明在一个实施例中提供了一种用于产生与系统时钟同步的时钟相位的结构，方法和装置，其中第一阶与工艺参数无关，包括驱动电流，寄生电阻和寄生电容。 在一个方面，提供了一种装置，用于在相对于输入时钟信号的预定时间产生输出相位，并取决于输入时钟信号的逻辑相位宽度。 在另一方面，该装置包括具有不等单位的类似电路部件，预定时间进一步取决于类似电路部件的单位比率。 在另一方面，该装置与装置的至少一个再现级联，并且被配置为提供输入时钟信号的倍数。 在另一方面，该装置与装置的至少一个再现并行耦合，并且被配置为在输入时钟信号期间提供并行产生的至少两个输出相位。
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