公开(公告)号：US09299424B2

公开(公告)日：2016-03-29

申请号：US14002874

申请日：2011-10-26

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G11C13/00 ,  G11C11/56

CPC分类号： G11C13/0002 ,  G11C11/56 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/74 ,  G11C2213/79

摘要： A reconfigurable circuit (10) according to the present invention includes: a switching element group that is formed by a plurality of switching elements (1), an ON state and an OFF state of the switching element being rewritable in accordance with a resistive state; and a configuration controller (60) that senses the resistive state of each of the switching elements and programs each switching element, wherein the configuration controller (60) senses the resistive state of each switching element (1) by applying an inspection-purpose voltage across the opposite electrodes of the switching element (1), and when the sensed resistive state is abnormal, the configuration controller applies a programming voltage across the opposite electrodes of the switching element such that the resistive state of the switching element becomes the programmed resistive state.

摘要翻译： 根据本发明的可重构电路（10）包括：由多个开关元件（1）形成的开关元件组，所述开关元件的导通状态和断开状态根据电阻状态是可重写的; 以及配置控制器（60），其感测每个开关元件的电阻状态并对每个开关元件进行编程，其中配置控制器（60）通过施加检查用电压来检测每个开关元件（1）的电阻状态 开关元件（1）的相对电极，并且当感测到的电阻状态异常时，配置控制器跨越开关元件的相对电极施加编程电压，使得开关元件的电阻状态变为编程电阻状态。

公开(公告)号：US20130009753A1

公开(公告)日：2013-01-10

申请号：US13637823

申请日：2011-02-08

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G06K7/01

CPC分类号： H04Q9/00 ,  B25J13/081 ,  G01D18/00 ,  G01D21/00 ,  G06K19/0717 ,  H04Q2209/47

摘要： A radio tag sensor system includes a plurality of radio tag sensor chips, which incorporate respective sensors, store unique identification numbers, a plurality of micro base stations, and a central processing unit which perform communications with the micro base stations via a connection network. Each of the micro base stations performs wireless communications with and wirelessly supplies electric power to only those of the radio tag sensor chips which are disposed in an assigned region thereof. Each of the assigned regions includes at least one radio tag sensor chip which is not included in the other assigned regions. The central processing unit controls the communications via the connection network. The central processing unit collects the sensed values from sensors of the radio tag sensor chips through the micro base stations, generates a spatial distribution map of the sensed values, and updates the spatial distribution map with time.

摘要翻译： 无线电标签传感器系统包括多个无线电标签传感器芯片，其包含各自的传感器，存储唯一的标识号，多个微型基站和经由连接网络与微型基站进行通信的中央处理单元。 微基站中的每一个都执行无线通信，并且仅将电力提供给仅布置在其分配区域中的无线电标签传感器芯片的电力。 每个分配的区域包括至少一个不包括在其他分配区域中的无线电标签传感器芯片。 中央处理单元通过连接网络控制通信。 中央处理单元通过微基站收集来自无线电标签传感器芯片的传感器的感测值，生成感测值的空间分布图，随时间更新空间分布图。

公开(公告)号：US20110225558A1

公开(公告)日：2011-09-15

申请号：US13130215

申请日：2009-11-27

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented.

摘要翻译： 一种可重构电路生成装置，其特征在于，具备：网表生成部，其生成作为共享网表的多个网表之间能够共享的网表，所述网表可以具有公共部分的多个网表之间共享;以及资源减少部，其减少所述可重配置电路的资源， 将在实现共享网表的范围内实现。

公开(公告)号：US20140347095A1

公开(公告)日：2014-11-27

申请号：US14363839

申请日：2012-12-13

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19/173 ,  H03K19/094

CPC分类号： H03K19/1737 ,  H03K19/018592 ,  H03K19/09429

摘要： Bidirectional buffer 20D includes: multiplexer 30 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each input terminal; tristate buffer 51 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each output terminal and that receives the output of multiplexer 30 as input; demultiplexer 31 that receives the output of tristate buffer 51 as input; programming transistor tr0 whose drain terminal is connected to the input terminal of tristate buffer 51; and programming transistor tr1 whose drain terminal is connected to the output terminal of tristate buffer 51. Input terminals i1 and i3 of multiplexer 30 are connected to respective output terminals t1 and t2 of demultiplexer 31.

摘要翻译： 双向缓冲器20D包括：多路复用器30，其配备有用于每个输入端子的可重写可变电阻非易失性开关元件; 三态缓冲器51，其配备有用于每个输出端子的可重写可变电阻非易失性开关元件，并且接收多路复用器30的输出作为输入; 接收作为输入的三态缓冲器51的输出的解复用器31; 编程晶体管tr0，其漏极端子连接到三态缓冲器51的输入端; 以及编程晶体管tr1，其漏极端子连接到三态缓冲器51的输出端。多路复用器30的输入端子i1和i3连接到解复用器31的各个输出端子t1和t2。

公开(公告)号：US20130176051A1

公开(公告)日：2013-07-11

申请号：US13821892

申请日：2011-08-18

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H01L27/101 ,  H03K19/177 ,  H03K19/17744 ,  H03K19/17748

摘要： A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmable wiring group. The reconfigurable circuit is also characterized in being provided with a fourth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the functional block input wiring group, and/or a fifth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the branch lines of the functional block output wiring.

摘要翻译： 本发明的可重构电路的特征在于具有：沿第一方向设置的第一可编程布线组; 第二可编程布线组，其沿与第一方向相交的第二方向设置; 第一开关元件阵列，其在功能块输入布线组的第一可编程布线组和分支线组的交叉点处或在第一可编程布线组的分支线组的交叉点处，在第一 可编程接线组和功能块输入接线组; 第二开关元件阵列，其在第一可编程布线组和功能块输出布线的交叉点处将可编程布线组彼此连接; 以及第三开关元件阵列，其在第二可编程布线组和第一可编程布线组的交叉点处将可编程布线组彼此连接。 可重构电路的特征还在于具有第四开关元件阵列，该第四开关元件阵列在第二可编程布线组和功能块输入布线组的交叉点处将可编程布线组彼此连接，和/或第五开关元件 阵列，其在第二可编程布线组和功能块输出布线的分支线的交叉点处将可编程布线组彼此连接。

公开(公告)号：US20120247534A1

公开(公告)日：2012-10-04

申请号：US13515473

申请日：2010-12-13

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H01L31/052

CPC分类号： H01L31/0543 ,  F24S23/31 ,  Y02E10/40 ,  Y02E10/52

摘要： A solar power generation apparatus in which a solar cell unit is disposed at focal position in an optical system, which includes a single optical system and formulated so as to collect and spectrally separate incident light that falls in parallel to an optical axis, and focus each of the spectrally separated wavelength band lights at a different focal position on the optical axis. The solar cell unit includes a plurality of solar cells, each including, a junction unit disposed on a circumference of a substrate portion disposed along the optical axis, a surface of the junction portion forming a light receiving surface with a different sensitive wavelength band. The plurality of solar cells are arrayed along the optical axis, and each of the solar cells is disposed at one of the focal positions at which the wavelength band light corresponding to each the different sensitive wavelength band is focused.

摘要翻译： 一种太阳能发电装置，其中太阳能电池单元设置在光学系统中的焦点位置，该光学系统包括单个光学系统，并且被配置为收集并光谱分离与光轴平行落入的入射光，并且将每个 在光轴上的不同焦点位置处的光谱分离的波长带光。 太阳能电池单元包括多个太阳能电池，每个太阳能电池包括设置在沿着光轴设置的基板部分的圆周上的接合单元，该接合部分的表面形成具有不同灵敏波长带的光接收表面。 多个太阳能电池沿着光轴排列，并且每个太阳能电池被配置在与各个不同灵敏波长带对应的波长带对焦的焦点位置之一处。

公开(公告)号：US20090031113A1

公开(公告)日：2009-01-29

申请号：US11920156

申请日：2006-05-09

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G06F9/32 ,  G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/223 ,  G06F9/26 ,  G06F9/30178 ,  G06F9/3885 ,  G06F15/8007

摘要： A processor array including area-saving microprogram memories is provided. In the processor array, microprogram memories of a plurality of adjacent processor arrays are shared. Effective data and position information 13 on the effective data are stored in the shared microprogram memory 3, and effective data parts 11.1 to 11.3 including effective data are accommodated with each other in logic blocks 2a and 2b of a plurality of processor elements. The number of necessary microprogram memories is thereby reduced, thus realizing area saving.

摘要翻译： 提供了包括节省区域的微程序存储器的处理器阵列。 在处理器阵列中，共享多个相邻处理器阵列的微程序存储器。 有效数据上的有效数据和位置信息13存储在共享微程序存储器3中，并且包括有效数据的有效数据部分11.1至11.3彼此容纳在多个处理器元件的逻辑块2a和2b中。 由此减少所需的微程序存储器的数量，从而实现区域节省。

公开(公告)号：US07191205B2

公开(公告)日：2007-03-13

申请号：US10968554

申请日：2004-10-18

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G06F7/50 ,  H03K19/20

CPC分类号： G06F7/501 ,  G06F7/523 ,  H03K19/1736

摘要： A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

摘要翻译： 功能块允许使用少量块实现乘法器和多输入多路复用器。 逻辑功能发生器根据从多个4输入/ 1输出逻辑功能中选择的逻辑功能，根据配置数据，从其第一至第四逻辑输入端生成逻辑输出信号。 4-2进位块产生从第二到第四逻辑输入的4-2进位输出。 第一信号至少从逻辑输出产生，来自至少第一逻辑输入的第二信号，来自至少4-2进位输入信号的第三信号和至少4-2进位输入的第四信号 信号。 多路复用器根据第一信号选择第二和第三信号之一以产生进位输出信号。 异或电路产生逻辑输出和第四信号的异或运算结果。

公开(公告)号：USRE37621E1

公开(公告)日：2002-04-02

申请号：US09413827

申请日：1999-10-06

申请人： Naoya Henmi ,  Shogo Nakaya ,  Tomoki Saito

发明人： Naoya Henmi ,  Shogo Nakaya ,  Tomoki Saito

IPC分类号： H04B1016

CPC分类号： G02B6/29377 ,  H04B10/25133 ,  H04B10/25253 ,  H04B10/2935

摘要： An optical communication transmission system including an optical amplifier lumped repeater system of the present invention includes, for the purpose of preventing degradation of the transmission characteristic arising from wavelength dispersion of optical fibers due to raised power of the optical signal, transmission optical fibers provided for all or most of the repeating sections and having wavelength dispersion values set to different values from zero, and optical fibers provided for the individual sections to compensate for the sum of wavelength dispersion of the sections so as to reduce the total wavelength dispersion to zero. The optical fiber for compensation for each section may be replaced by a substitutive compensation element. Alternatively, very small wavelength dispersion which remains due to failure in compensating to zero dispersion may be compensated for using a dispersion equalizer of an electric system in the reception section.

摘要翻译： 包括本发明的光放大器集总中继器系统的光通信传输系统包括为了防止由于光信号的提高功率而导致的光纤的波长色散引起的传输特性的劣化，为全部提供的传输光纤 或大部分重复部分，并且将波长色散值设定为与零不同的值，以及为每个部分提供的光纤以补偿部分的波长色散之和，以将总波长色散减小至零。 用于每个部分的补偿的光纤可以由替代补偿元件代替。 或者，可以使用接收部分中的电气系统的色散均衡器来补偿由于补偿零色散失败而保留的非常小的波长色散。

公开(公告)号：US09106231B2

公开(公告)日：2015-08-11

申请号：US14363839

申请日：2012-12-13

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19/177 ,  H01L25/00 ,  H03K19/173 ,  H03K19/0185 ,  H03K19/094

CPC分类号： H03K19/1737 ,  H03K19/018592 ,  H03K19/09429

摘要： Bidirectional buffer 20D includes: multiplexer 30 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each input terminal; tristate buffer 51 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each output terminal and that receives the output of multiplexer 30 as input; demultiplexer 31 that receives the output of tristate buffer 51 as input; programming transistor tr0 whose drain terminal is connected to the input terminal of tristate buffer 51; and programming transistor tr1 whose drain terminal is connected to the output terminal of tristate buffer 51. Input terminals i1 and i3 of multiplexer 30 are connected to respective output terminals t1 and t2 of demultiplexer 31.

摘要翻译： 双向缓冲器20D包括：多路复用器30，其配备有用于每个输入端子的可重写可变电阻非易失性开关元件; 三态缓冲器51，其配备有用于每个输出端子的可重写可变电阻非易失性开关元件，并且接收多路复用器30的输出作为输入; 接收作为输入的三态缓冲器51的输出的解复用器31; 编程晶体管tr0，其漏极端子连接到三态缓冲器51的输入端; 以及编程晶体管tr1，其漏极端子连接到三态缓冲器51的输出端。多路复用器30的输入端子i1和i3连接到解复用器31的各个输出端子t1和t2。