公开(公告)号：US06670826B1

公开(公告)日：2003-12-30

申请号：US10133089

申请日：2002-04-26

申请人： Trevor J. Bauer

发明人： Trevor J. Bauer

IPC分类号： H03K1977

CPC分类号： H03K19/17728

摘要： A configurable logic block for a programmable logic device includes a storage element having a latch clocked by a write strobe pulse. The storage element uses a write strobe signal and, optionally, a hold signal already present in the CLB. In one embodiment, the CLB includes a function generator, a write strobe generator providing hold and write strobe signals to the function generator, and a storage element driven by the function generator output signal and by the hold and write strobe signals from the write strobe generator. Because the CLB already includes a write strobe generator, it is not necessary to design additional logic to avoid race conditions in the storage element.

摘要翻译： 用于可编程逻辑器件的可配置逻辑块包括具有由写选通脉冲进行时钟脉冲的锁存器的存储元件。 存储元件使用写入选通信号，并且可选地使用已经存在于CLB中的保持信号。 在一个实施例中，CLB包括函数发生器，写入选通发生器，向函数发生器提供保持和写选通信号，以及由函数发生器输出信号驱动的存储元件以及来自写选通发生器的保持和写选通信号 。 因为CLB已经包括一个写选通发生器，所以不需要设计额外的逻辑来避免存储元件中的竞争条件。

公开(公告)号：US06486703B2

公开(公告)日：2002-11-26

申请号：US09756099

申请日：2001-01-08

申请人： Wendell P. Noble ,  Leonard Forbes

发明人： Wendell P. Noble ,  Leonard Forbes

IPC分类号： H03K1977

CPC分类号： H01L27/11803

摘要： A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

摘要翻译： 提供可编程逻辑阵列。 可编程逻辑阵列包括第一和第二逻辑平面。 第一逻辑平面接收多个输入信号。 第一逻辑平面包括互连以提供多个逻辑输出的以行和列排列的多个垂直晶体管。 第二逻辑平面还包括排列成行和列的多个垂直晶体管，其接收第一逻辑平面的输出并互连以产生多个逻辑输出，使得可编程逻辑阵列实现逻辑功能。

公开(公告)号：US06392438B1

公开(公告)日：2002-05-21

申请号：US09684148

申请日：2000-10-06

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

IPC分类号： H03K1977

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

摘要翻译： 可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US06653861B1

公开(公告)日：2003-11-25

申请号：US10023053

申请日：2001-12-14

申请人： Om P. Agrawal ,  Jinghui Zhu

发明人： Om P. Agrawal ,  Jinghui Zhu

IPC分类号： H03K1977

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17744

摘要： A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may have a partially populated first level for programmably routing signals from the I/O cells into a first set of output signals. A second level of the routing structure programmably routes signals from the first set of output signals to I/O cells in the routing structure's I/O block.

摘要翻译： 包括布置在I / O块中的多个I / O单元的可编程互连电路包括用于每个I / O块的路由结构，其中每个路由结构可以具有部分填充的第一级，用于可编程地路由来自I / O单元的信号 成为第一组输出信号。 路由结构的第二级可编程地将来自第一组输出信号的信号路由到路由结构的I / O块中的I / O单元。

公开(公告)号：US06556500B2

公开(公告)日：2003-04-29

申请号：US10033976

申请日：2001-12-26

申请人： Francis B. Heile

发明人： Francis B. Heile

IPC分类号： H03K1977

CPC分类号： H03K19/1776 ,  H03K19/17704 ,  H03K19/17728

摘要： A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory (“RAM”) or to perform product term (“p-term”) logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

公开(公告)号：US06459297B1

公开(公告)日：2002-10-01

申请号：US09399571

申请日：1999-09-20

申请人： David A. Smiley

发明人： David A. Smiley

IPC分类号： H03K1977

CPC分类号： G06F17/5054

摘要： A system for programming field programmable devices (FPDs) of different types across different boards. An in-system programmable master (ISPM) communicates over a bus to in-system programmable slaves (ISPSs) on one or more boards. FPDs on each board are connected into chains of the same type, and each chain is connected to an ISPS located on the board. The ISPM uses a packet protocol to communicate with all ISPSs in a system. Each packet comprises an ISPS address field, a chain select field, and a command field. Each ISPS reads packets addressed to it, and decodes and transmits the commands to the selected FPD chain in a protocol appropriate to the chain.

摘要翻译： 用于在不同电路板上编程不同类型的现场可编程器件（FPD）的系统。 系统内可编程主机（ISPM）通过总线通信到一个或多个电路板上的系统可编程从机（ISPS）。 每个板上的FPD连接成相同类型的链，每个链连接到位于板上的ISPS。 ISPM使用数据包协议与系统中的所有ISPS进行通信。 每个分组包括ISPS地址字段，链选择字段和命令字段。 每个ISPS读取寻址到它的数据包，并在适用于链路的协议中解码并将命令传输到选定的FPD链。