公开(公告)号：US06653956B2

公开(公告)日：2003-11-25

申请号：US09906816

申请日：2001-07-18

申请人： Sanroku Tsukamoto

发明人： Sanroku Tsukamoto

IPC分类号： H03M716

CPC分类号： H03M1/0687 ,  H03M1/0809 ,  H03M1/1095 ,  H03M1/365 ,  H03M13/47

摘要： A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

公开(公告)号：US06703951B2

公开(公告)日：2004-03-09

申请号：US09906797

申请日：2001-07-18

申请人： Sanroku Tsukamoto

发明人： Sanroku Tsukamoto

IPC分类号： H03M716

CPC分类号： H03M1/0687 ,  H03M1/0809 ,  H03M1/1095 ,  H03M1/365 ,  H03M13/47

摘要： A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

摘要翻译： 高速A / D转换器包括用于将温度计代码转换为灰度代码的一系列编码器部分和用于检测灰度代码中的错误信号的误差信号产生部分，并产生指示这种混淆误差的误差信号。 误差校正部分根据误差信号校正灰度代码中的错误。 然后将经校正的灰度码转换为具有灰度码的二进制码到二进制码转换器。 当将高速A / D转换器并入半导体器件中时，可以使用具有相对于输入模拟信号连续变化的相位的采样时钟来测试A / D转换器，以对模拟信号进行采样，然后评估 相应产生的数字信号。

公开(公告)号：US06703950B2

公开(公告)日：2004-03-09

申请号：US09951783

申请日：2001-09-14

申请人： Cheng Yi

发明人： Cheng Yi

IPC分类号： H03M716

CPC分类号： H03M7/16

摘要： The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

摘要翻译： 本发明包括对小于全长的二进制和格雷码序列进行格雷编码/解码的方法，导致几何上减少的存储要求。

公开(公告)号：US06762701B2

公开(公告)日：2004-07-13

申请号：US10320282

申请日：2002-12-16

申请人： Hongtao Jiang Jiang

发明人： Hongtao Jiang Jiang

IPC分类号： H03M716

CPC分类号： H03M7/16 ,  G06F5/10 ,  G06F2205/102 ,  H03K23/005

摘要： A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed. One embodiment of the Gray-code counter of this invention comprises a Gray-to-binary converter for receiving an M-bit Gray-code input value and converting the M-bit Gray-code input value to an M-bit binary-code input value, IB[m−1:0]; a binary incrementer-decrementer for converting the M-bit binary-code input value to an M-bit binary-code output value, OB[m−1:0], wherein the M-bit binary-code output value will differ from the M-bit binary-code input value by modulo +/−1 for all but one value of the M-bit binary-code input value; a binary-to-Gray converter for converting the M-bit binary-code output value to an M-bit Gray-code output value; and a clocked storage device operably coupled to the binary-to-Gray converter for storing the M-bit Gray-code output value and for providing the M-bit Gray-code output value to the Gray-to-binary converter as a next M-bit Gray-code input value. The binary incrementer-decrementer further comprises an incrementer-decrementer algorithm for skipping certain binary values in order to maintain the Gray-code nature of the counter when translated to Gray-code, while allowing the Gray-code counter to be implemented as a modulo counter of any even size.

摘要翻译： 公开了一个非二分之一模N格雷码计数器（“格雷码计数器”）和二进制减法器算法。 本发明的格雷码计数器的一个实施例包括用于接收M比特格雷码输入值并将M比特格雷码输入值转换为M位二进制码输入的格雷二进制转换器 值，IB [m-1：0]; 用于将M位二进制代码输入值转换为M位二进制代码输出值OB [m-1：0]的二进制增量递减器，其中M位二进制代码输出值将不同于 M位二进制码输入值除了M位二进制码输入值的一个值外，均为模数+/- 1; 用于将M位二进制码输出值转换为M位格雷码输出值的二进制到灰色转换器; 以及可操作地耦合到二进制到灰色转换器的时钟存储装置，用于存储M位格雷码输出值，并用于将灰度到二进制转换器的M位格雷码输出值提供为下一个M 位格雷码输入值。 二进制递增器减法器还包括用于跳过某些二进制值的递增器递减器算法，以便在转换为格雷码时保持计数器的格雷码特性，同时允许将格雷码计数器实现为模计数器 任何均匀的尺寸。

公开(公告)号：US06262676B1

公开(公告)日：2001-07-17

申请号：US09368585

申请日：1999-08-05

申请人： Douglas B.S. King

发明人： Douglas B.S. King

IPC分类号： H03M716

CPC分类号： G06K9/6202 ,  G06F7/026 ,  G06N3/063 ,  G06T5/20 ,  H03M7/16 ,  H03M7/165

摘要： A thermometer code converter for converting weightless binary tuples of 2 or higher dimensional arrays into a thermometer or aggregate code comprises a series of layers (16, 18) each made up of bit manipulation cells (10) which collectively cause set bits to be shifted towards a required bit position. The bit manipulation cells are made up of logic elements (12, 14) and the entire converter may be asynchronous. Also disclosed is a sum and threshold device which employs a thermometer code converter and a bit selector device.

摘要翻译： 一种用于将2维或更高维度阵列的重量二进制元组转换为温度计或聚合代码的温度计代码转换器包括一系列由位操作单元（10）构成的层（16,18），这些位组合使得设置位向着 所需位位置。 位操作单元由逻辑元件（12,14）组成，并且整个转换器可以是异步的。 还公开了采用温度计代码转换器和位选择器装置的和值和阈值装置。