公开(公告)号：US06233256B1

公开(公告)日：2001-05-15

申请号：US08816457

申请日：1997-03-12

申请人： Charles Benjamin Dieterich ,  Arthur Lee Greenberg

发明人： Charles Benjamin Dieterich ,  Arthur Lee Greenberg

IPC分类号： H04J307

CPC分类号： H04L43/0847 ,  H04J3/0632 ,  H04L43/00 ,  H04L43/045 ,  H04L43/06 ,  H04L43/087 ,  H04L43/0882 ,  H04L43/0888 ,  H04L43/106 ,  H04L43/18 ,  H04L2012/5616 ,  H04L2012/5636 ,  H04L2012/5674 ,  H04L2012/5684 ,  H04Q11/0478

摘要： A method and apparatus for analyzing and monitoring packet streams in “real time”. The packet analyzer comprises an input buffer, a real-time analysis unit, a non-real-time analysis unit, a graphics unit, a monitor and a flushing circuit. A packet stream is received into the input buffer where the data is either read by the real-time analysis unit or flushed by the flushing circuit. Messages are passed between the real-time analysis unit and the non-real-time analysis unit to report on detected errors or to update packet stream information. In turn, real time packet stream information are displayed and updated on a display via the graphic unit. A method of detecting framing errors in a packet stream is incorporated by setting a 9th bit in the input buffer for each byte of data in a packet.

摘要翻译： 一种用于“实时”分析和监视分组流的方法和装置。 分组分析器包括输入缓冲器，实时分析单元，非实时分析单元，图形单元，监视器和冲洗电路。 分组流被接收到输入缓冲器中，其中数据被实时分析单元读取或被冲洗电路冲洗。 消息在实时分析单元和非实时分析单元之间传递，以报告检测到的错误或更新分组流信息。 反过来，通过图形单元在显示器上显示和更新实时分组流信息。 通过在分组中为数据的每个字节设置输入缓冲器中的第9位来合并检测分组流中的成帧错误的方法。

公开(公告)号：US06493359B1

公开(公告)日：2002-12-10

申请号：US09305248

申请日：1999-05-04

申请人： Alan M. Sorgi ,  Scott A. Applebaum

发明人： Alan M. Sorgi ,  Scott A. Applebaum

IPC分类号： H04J307

CPC分类号： H04J3/1611 ,  H04J3/0685

摘要： The invention provides an apparatus, and related method, for providing a reconfigurable frame counter that can accommodate differing start of frame pulse locations in a synchronous communication system. The frame counter may be integrated with existing devices thus providing a cost effective advance in the functionality of existing communication devices. The reconfigurable frame counter includes a multiplexer, a byte processor and a frame counter. The multiplexer byte interleave multiplexes a plurality of lower data rate SONET signals to generate a higher data rate SONET signal of framed data bytes. The byte processor processes transport overhead bytes of the higher data rate SONET signal in accordance with a frame byte count value. The frame byte counter counts clock pulses that are each associated with the arrival of a framed data byte and generates a frame byte count value that corresponds to a frame byte location of the currently received framed data byte. The frame byte counter has a programmable configuration start address value and a synchronization pulse input and, in response to a synchronization pulse on the synchronization pulse input, the frame byte counter counts the clock pulses with an initial start count equal to the configuration start address value such that the frame byte count value indicates the frame byte location of the currently received framed data byte.

摘要翻译： 本发明提供了一种用于提供可配置帧计数器的装置和相关方法，其可以适应同步通信系统中帧脉冲位置的不同开始。 帧计数器可以与现有设备集成，从而为现有通信设备的功能提供了成本有效的推进。 可重构帧计数器包括多路复用器，字节处理器和帧计数器。 复用器字节交错多个较低数据速率SONET信号以产生成帧数据字节的较高数据速率SONET信号。 字节处理器根据帧字节计数值处理较高数据速率SONET信号的传输开销字节。 帧字节计数器计数每个与成帧数据字节的到达相关联的时钟脉冲，并产生对应于当前接收的成帧数据字节的帧字节位置的帧字节计数值。 帧字节计数器具有可编程配置开始地址值和同步脉冲输入，并且响应于同步脉冲输入上的同步脉冲，帧字节计数器对初始启动计数等于配置开始地址值的时钟脉冲进行计数 使得帧字节计数值指示当前接收的成帧数据字节的帧字节位置。

公开(公告)号：US06381243B1

公开(公告)日：2002-04-30

申请号：US09156654

申请日：1998-09-18

申请人： Ulf Ekstedt

发明人： Ulf Ekstedt

IPC分类号： H04J307

CPC分类号： H04Q11/0478 ,  H04L2012/5673 ,  H04L2012/5674

摘要： A time slot aligner (60) determines delay (in terms of frames) of time slots of a set of frames received on Plesiochronous Digital Hierarchy (PHD) transmission network. In accordance with the time slot frame/delay determination technique of the invention, the time slot aligner finds an initial header of an ATM cell by searching five consecutive time slots in nearby frames of the set of frames. Once the initial header is found, a frame/delay value is determined for each time slot comprising the header. The frame/delay values for selected time slots of the header are then used to form a window which is used for searching for the next header. Searching for a next header for a next ATM cell involves sliding the window to other frames of the set of frames and searching for a value in a successive time slot which will form a HEC byte for a header framed by the sliding window. When a next header is located, a frame/delay determination has to be made only for the last time slot of the header, e.g., the time slot which formed the HEC byte. A new window is then formed using the frame/delay pattern from the most-recently acquired header, and that new window slid to find yet another header. Header location, time slot frame/delay determination, and formation of a new window continue until a frame/delay determination is made for all time slots of the set of frames.

摘要翻译： 时隙对准器（60）确定在同步数字体系（PHD）传输网络上接收的一组帧的时隙的延迟（以帧为单位）。 根据本发明的时隙帧/延迟确定技术，时隙对准器通过搜索该组帧的附近帧中的五个连续时隙来找到ATM信元的初始报头。 一旦找到初始报头，就为包含报头的每个时隙确定帧/延迟值。 然后，头部的选定时隙的帧/延迟值用于形成用于搜索下一个报头的窗口。 搜索下一个ATM信元的下一个标题包括将窗口滑动到该组帧的其他帧，并搜索连续时隙中的值，该值将形成由滑动窗口构成的标题的HEC字节。 当定位下一个报头时，必须仅对报头的最后一个时隙进行帧/延迟确定，例如形成HEC字节的时隙。 然后使用来自最近获取的头部的帧/延迟图案形成新窗口，并且该新窗口滑动以找到另一个标题。 标题位置，时隙帧/延迟确定和新窗口的形成继续，直到对该组帧的所有时隙进行帧/延迟确定。

公开(公告)号：US06763036B1

公开(公告)日：2004-07-13

申请号：US09275625

申请日：1999-03-24

申请人： Michael F. Maas ,  Edward L. Grivna

发明人： Michael F. Maas ,  Edward L. Grivna

IPC分类号： H04J307

CPC分类号： H04L7/042 ,  H03M9/00

摘要： An apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.

摘要翻译： 一种装置，包括寄存器电路，检测器电路和输出电路。 寄存器电路可以被配置为响应于（i）串行输入和（ii）第一时钟而呈现并行信号。 检测器电路可以被配置为响应于（i）并行信号和（ii）选择信号而产生控制信号。 输出电路可以被配置为响应于（i）控制信号和（ii）并行信号而产生输出。

公开(公告)号：US06738393B2

公开(公告)日：2004-05-18

申请号：US09171216

申请日：1998-10-13

申请人： Toshio Miki ,  Sanae Hotani

发明人： Toshio Miki ,  Sanae Hotani

IPC分类号： H04J307

CPC分类号： H04J3/0608 ,  H04L7/08

摘要： In a frame synchronization circuit, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system, the frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code. The frame synchronization circuit is also provided with and a data loss and data insertion period judgment circuit which determines which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.

摘要翻译： 在帧同步电路中，根据常规数据传输系统中的典型代码错误，防止由于数据丢失/插入而导致的同步误差的发生同时抑制错误同步/失步，帧同步电路具有帧 同步码检测器，其从接收的数据序列检测帧同步码以输出帧位置，并通过检查检测到的帧同步码和正确的帧同步码来输出检查结果。 帧同步电路还具有数据丢失和数据插入周期判断电路，该电路根据检查结果确定哪个是假定在接收的数据序列中是否发生了数据丢失或数据插入。

公开(公告)号：US06577639B1

公开(公告)日：2003-06-10

申请号：US09323983

申请日：1999-06-01

申请人： Brooks S. Read

发明人： Brooks S. Read

IPC分类号： H04J307

CPC分类号： H04J3/07

摘要： A method for assuring that samples are always available for transmission when a modern is implemented as a process executing in the memory of a host computer. The modem process converts, digital information into transmit data samples. In the absence of digital information, the modem process converts fill data into fill data samples. The transmit data samples and fill data samples are stored in a segmented buffer for transmission to a remote modem. If additional transmit data samples become available and the buffer contains fill data samples which have not been transmitted to the remote modem, the modem process replaces the fill data samples in the buffer with the additional transmit data samples. The method helps assure that samples are always available for transmission, and simultaneously reduces the time delay or latency between when data enter the modem and when the data are subsequently transmitted.

摘要翻译： 当将现代实现为在主机的存储器中执行的处理时，确保样本总是可用于传输的方法。 调制解调器过程将数字信息转换为发送数据样本。 在没有数字信息的情况下，调制解调器过程将填充数据转换为填充数据样本。 发送数据样本和填充数据样本存储在分段缓冲器中，以传输到远程调制解调器。 如果附加的发送数据样本可用，并且缓冲器包含尚未发送到远程调制解调器的填充数据样本，则调制解调器进程用附加的发送数据样本替换缓冲器中的填充数据样本。 该方法有助于确保样本始终可用于传输，并且同时减少数据进入调制解调器和数据随后传输时间之间的时间延迟或延迟。

公开(公告)号：US06442177B1

公开(公告)日：2002-08-27

申请号：US09155424

申请日：1998-09-29

申请人： Bertrand DeBray

发明人： Bertrand DeBray

IPC分类号： H04J307

CPC分类号： H04J3/12 ,  H04J3/07

摘要： A method of inserting a service channel in frames that are plesiochronous relative to the service channel, the method including the steps of transmitting a block clock between a transmitter and a receiver of the frame, and reserving at the transmitter at least one location in the frames for the purpose of conveying the service channel data. The method further includes the steps of: inserting blocks (B) of the service channel into the reserved location causing each of the blocks (B) to be preceded by a predetermined number n1 of identical bits (D) referred to as “start” bits, and to do so in compliance with the following rules: in the event of there being no need to pad out the remainder of the location, repeating the method from the inserting step for a new block (B); in the event of it being necessary to pad out the remainder of the location, causing each of the blocks (B) to be followed by a number n2 of identical bits (F) referred to as “stop” bits, the “stop” bits (F) being different from the start bits (D), and repeating the method from the inserting step for a new block (B); and at the receiver: detecting the regular arrival of the start bits (D) or the regular arrival of the start bits (D) preceded by the stop bits (F), so as to be able to decide that the blocks (B) are present in the reserved locations and to extract the blocks (B) from the reserved locations.

摘要翻译： 一种将业务信道插入到相对于服务信道相位同步的帧中的方法，所述方法包括以下步骤：在所述帧的发射机和接收机之间传输块时钟，并且在所述发射机处保留所述帧中的至少一个位置 用于传送服务频道数据。 该方法还包括以下步骤：将服务信道的块（B）插入保留位置，使得块（B）中的每一个前面加上被称为“起始”位的相同位（D）的预定数量n1 ，并按照以下规则执行：在不需要填补剩余部分的情况下，从新块（B）的插入步骤重复该方法; 在需要填补该位置的剩余部分的情况下，使得每个块（B）后面跟有被称为“停止”位的相同位（F）的数目n2，“停止”位 （F）与起始位（D）不同，并从新块（B）的插入步骤重复该方法; 并且在接收机处：检测起始比特（D）的定期到达或开始比特（D）的正常到达之前的停止比特（F），以便能够确定块（B）是 存在于预留位置并从预留位置提取块（B）。

公开(公告)号：US06804266B1

公开(公告)日：2004-10-12

申请号：US09491122

申请日：2000-01-24

申请人： Branko Kovacevic ,  Kevork Kechichian

发明人： Branko Kovacevic ,  Kevork Kechichian

IPC分类号： H04J307

CPC分类号： H04N21/44016 ,  H04J3/07 ,  H04N21/23424 ,  H04N21/23614 ,  H04N21/434 ,  H04N21/4348 ,  H04N21/435

摘要： In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream. In another embodiment, the hardware is used to implement a splicing of streams of data.

摘要翻译： 根据本发明的具体方面，诸如MPEG-2视频流的压缩视频流由传输解复用器接收，被同步，被解析成单独的分组类型，并被写入到解复用器外部的缓冲器位置。 适应字段由单独的解析器处理。 此外，主基本流数据可以基于主基本流的分组标识符由单独的主要基本流解析器来处理。 视频数据包可以基于流标识符值进行解析。 基于分配表信息，通过输出控制器将特定数据分组存储在一个或多个系统存储器或视频存储器缓冲器中。 与特定基本流或分组适配字段相关联的私有数据被重新分组，并被写入输出缓冲器位置。 在具体实现中，与系统相关联的硬件用于获取数据流，而不知道流的特定协议。 在另一个实施例中，硬件用于实现数据流的拼接。

公开(公告)号：US06400732B1

公开(公告)日：2002-06-04

申请号：US09384038

申请日：1999-08-26

申请人： Peter J. Castagna ,  David Randall

发明人： Peter J. Castagna ,  David Randall

IPC分类号： H04J307

CPC分类号： H04J3/0608 ,  H04J3/073

摘要： A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.

摘要翻译： 一种用于确定高速多路复用数据系统中同步和丢失同步的方法和装置。 该系统还包括多个对齐控制位和向后兼容标志，其允许系统与具有较少对齐控制位的旧系统一起操作。

公开(公告)号：US06385212B1

公开(公告)日：2002-05-07

申请号：US09182882

申请日：1998-10-30

申请人： Masayuki Baba ,  Yoshiaki Kato ,  Tokumichi Murakami

发明人： Masayuki Baba ,  Yoshiaki Kato ,  Tokumichi Murakami

IPC分类号： H04J307

CPC分类号： H04N21/23424 ,  H04N21/23611 ,  H04N21/2401

摘要： A data switching apparatus selects and transmits one of a plurality of received data and switches coded data while holding a coding unit of the coded data. A data switching apparatus includes plural data unit detectors each for detecting a coding unit of a data from a received data; plural data storages each for storing a received data in a buffer and transmitting the received data at a given time from a point specified by the data unit detector; and a data selecting unit for selecting and transmitting only one data stream from a plurality of data streams which are transmitted respectively from the plural data storages.

摘要翻译： 数据交换装置选择发送多个接收数据中的一个，并且在保存编码数据的编码单元的同时切换编码数据。 一种数据交换装置，包括：多个数据单元检测器，用于从接收到的数据中检测数据的编码单元; 多个数据存储器，用于将接收的数据存储在缓冲器中，并在给定时间从所述数据单元检测器指定的点发送所接收的数据; 以及数据选择单元，用于从分别从多个数据存储器发送的多个数据流中仅选择和发送一个数据流。