公开(公告)号：US06870231B2

公开(公告)日：2005-03-22

申请号：US10292180

申请日：2002-11-12

申请人： Sung-Bong Kim ,  Soon-Moon Jung ,  Jae-Kyun Park

发明人： Sung-Bong Kim ,  Soon-Moon Jung ,  Jae-Kyun Park

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H10L31/119

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode. The first node line is electrically connected to the second gate electrode through a first local interconnection crossing over the first node line, and the second node line is electrically connected to the first gate electrode through a second local interconnection crossing over the second node line. Additionally, a word line may be in direct contact with gate electrodes of transfer transistors of the SRAM cells.

摘要翻译： 提供SRAM单元和器件。 SRAM单元可以与相邻单元共享连接，包括地，电源电压和/或位线连接。 还提供了包括设置在半导体衬底上的第一和第二有源区的SRAM单元和器件。 平行的第一和第二栅电极跨过第一和第二有源区。 与第一栅极相邻的第一有源区的一端通过与第一栅电极平行的第一节点线与第一栅电极相邻的第二有源区电连接，并且与第一有源区相邻的第一有源区的另一端 第二栅电极通过与第二栅电极平行的第二节点线电连接到与第二栅电极相邻的第二有源区。 第一节点线通过跨第一节点线的第一局部互连电连接到第二栅极电极，并且第二节点线通过跨第二节点线的第二局部互连电连接到第一栅电极。 此外，字线可以与SRAM单元的转移晶体管的栅电极直接接触。

公开(公告)号：US06876028B1

公开(公告)日：2005-04-05

申请号：US10605444

申请日：2003-09-30

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

IPC分类号： H01L21/02 ,  H01L21/768 ,  H10L27/108 ,  H10L29/76 ,  H10L29/94 ,  H10L31/119

CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.