Frequency multiplier with balun function

    公开(公告)号:US12119825B2

    公开(公告)日:2024-10-15

    申请号:US17780618

    申请日:2019-12-10

    摘要: Frequency multipliers (300) for generating a differential output signal from a single-ended input signal are disclosed. The frequency multiplier comprises a single-ended input (Pin(f0)) to receive the input signal with a frequency of f0 and differential outputs (+/−Pout(2nf0)) to provide the differential output signals. The frequency multiplier further comprises a first signal branch (301) connected to the single-ended input and one of the differential outputs (+Pout(2nf0)). The first signal branch comprises a first low pass or bandpass filter with a center frequency of f0 (L/BPF1), a first nonlinear component (NC1) and a first high pass or bandpass filter with a center frequency of 2nf0 (H/BPF1). The frequency multiplier further comprises a second signal branch connected to the single-end input and another one of the differential outputs (−Pout(2nf0)). The second signal branch comprises a second low pass or bandpass filter with a center frequency of f0 (L/BPF1), a second nonlinear component (NC2) and a second high pass or bandpass filter with a center frequency of 2nf0 (H/BPF2). The first and second nonlinear components are configured such that even-order harmonics generated in the first and second nonlinear components are in anti-phase, thereby the differential output signals with a frequency of 2n times the frequency of the input signal are generated at the differential output, where n is an integer number.

    LOW PASS FILTER AND SEMICONDUCTOR DEVICE
    4.
    发明公开

    公开(公告)号:US20240258996A1

    公开(公告)日:2024-08-01

    申请号:US18423304

    申请日:2024-01-26

    申请人: ABLIC Inc.

    IPC分类号: H03H11/04 H03K17/687

    CPC分类号: H03H11/04 H03K17/687

    摘要: A low pass filter and a semiconductor device including the low pass filter are capable of quickly reaching a steady state upon power-on. The low pass filter includes a first first-conductivity-type MOS transistor, an electrostatic capacitor, a buffer circuit, a bias circuit, an input terminal, and an output terminal. The input terminal is connected to a source terminal of the first first-conductivity-type MOS transistor. A drain terminal of the first first-conductivity-type MOS transistor is connected to a first terminal of the electrostatic capacitor, the output terminal, and an input terminal of the buffer circuit. An output terminal of the buffer circuit is connected to an input terminal of the bias circuit. An output terminal of the bias circuit is connected to a gate terminal of the first first-conductivity-type MOS transistor.

    Clock generator and electronic device including the same

    公开(公告)号:US12040799B2

    公开(公告)日:2024-07-16

    申请号:US18154966

    申请日:2023-01-16

    摘要: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuit configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.

    Hybrid compensation system and control method thereof

    公开(公告)号:US12040764B2

    公开(公告)日:2024-07-16

    申请号:US18071755

    申请日:2022-11-30

    摘要: A hybrid compensation system is electrically connected between a power grid and a load. The hybrid compensation system includes an active filter, a passive filter and a control unit. The active filter generates an output current. The active filter includes a switching circuit, a DC bus capacitor and a filtering inductor. The control unit includes a voltage controller, a first reactive current detector, a harmonic current compensator, a current loop controller and a modulator. The voltage controller generates a first current given signal according to a bus voltage of the DC bus capacitor and a reference voltage. The first reactive current detector generates a second current given signal. The harmonic current compensator generates a third current given signal. The current loop controller generates a control signal. The modulator generates a driving signal according to the control signal.

    BAND PASS FILTER AND RECEIVER MODULE
    8.
    发明公开

    公开(公告)号:US20240171153A1

    公开(公告)日:2024-05-23

    申请号:US18114549

    申请日:2023-02-27

    发明人: Eunhyuk KWAK

    IPC分类号: H03H11/04

    CPC分类号: H03H11/04

    摘要: A band pass filter includes a resonator including a first inductor and a first capacitor coupled in series between a first port and a second port, a second inductor coupled in parallel with the resonator, a second capacitor coupled in parallel with the resonator, and a third capacitor coupled between one end of the second capacitor and the ground to perform a low pass filter function.

    Transceiver and calibration method

    公开(公告)号:US11990931B2

    公开(公告)日:2024-05-21

    申请号:US17929750

    申请日:2022-09-06

    发明人: Yi-Shao Chang

    IPC分类号: H04B1/40 H03H11/04 H04B17/11

    CPC分类号: H04B1/40 H03H11/04 H04B17/11

    摘要: A transceiver includes a RF modulator, a filter circuit, a control circuit and a first DC offset compensation circuit. During a first calibration period, the control circuit controls the filter circuit to be connected to the RF modulator with a first phase sequence, such that the RF modulator outputs a first radio frequency signal. During a second calibration period, the control circuit controls the filter circuit to be connected to the RF modulator with a second phase sequence, such that the RF modulator outputs a second radio frequency signal. The second phase sequence is inverted with the first phase sequence. The control circuit is further configured to calculate a first DC offset generated from the filter circuit, and to control the first DC offset compensation circuit to compensate the first DC offset generated from the filter circuit.