公开(公告)号：WO1998014955A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017552

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WENDELL, Dennis, L.

IPC: G11C29/00

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

Abstract translation: 导致存储单元负载装置不起作用的制造缺陷常常难以测试。 这样一个有缺陷的存储器单元可以被写入并随后读取成功，即使没有丢失的负载设备。 但是如果写入和后续读取之间的延迟足够长，则内存单元的内部节点会泄漏到降级的高电平，只有存储单元才会失败。 检测到这种故障所需的延迟可能容易达到数十秒，这完全不符合制造测试的所需经济性。 数据保持电路和方法允许对静态存储器单元进行高速测试，以确保单元内的负载装置实际存在和运行。 模拟字线驱动能力允许有源字线被驱动到用户可控的模拟电平。 这通过将行解码器的最终PMOS级的“VDD”和N阱连接到组装时通常连接到VDD的隔离端子来实现，但是在封装之前可以独立使用。 通过降低与存储器阵列电源电压相比的模拟字线电压，在缺少负载装置的存储单元中写入的高电平不会被拉高（因为所讨论的负载装置丢失），并且已经足够低以致导致 后续阅读立即失败。 因此，可以测试存储器阵列，而不需要在每个存储器单元的写入和读取之间的长时间延迟。 有利地，行和列支持电路和感测电路在它们被设计的正常电源电平下工作，并且可以独立地进行裕度测试。

公开(公告)号：WO1998014956A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017635

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WENDELL, Dennis, L.

IPC: G11C29/00

CPC classification number: G11C29/026 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

Abstract translation: 公开了存储器阵列测试和表征能力，其允许存储器单元，位线和读出放大器的DC表征。 提供行解码器，其包括静态字线选择信号以禁止行解码器内的自复位逻辑，并允许字线在用户控制的时间长度上保持有效。 模拟字线驱动能力允许有源字线被驱动到用户可控的模拟电平。 直接访问一对位线由多路复用器提供，多路复用器被静态解码以将一对隔离终端耦合到解码列内的相应位线。 这允许在解码列内和/或两个位线电流中的每个位线上施加直流电压电平以被感测。 为存储器阵列提供单独的电源连接，其允许以与电路的其余部分不同的电源电压操作存储器阵列。 通过将这些特征中的一个或多个一起使用，可以执行存储器阵列的若干测试，包括表征存储器单元的DC传递函数，存储器阵列的待机功率，存储器单元的静态噪声容限， 作为存储单元电源电压的函数的存储器单元的粒子敏感性，位线读出放大器的偏移电压等。