公开(公告)号：WO2020242527A1

公开(公告)日：2020-12-03

申请号：PCT/US2019/066662

申请日：2019-12-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LEE, Seungpil ,  KIM, Kwang-Ho

IPC: H01L21/66 ,  H01L23/544 ,  H01L27/06 ,  H01L23/00 ,  G06F3/06

Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad

公开(公告)号：WO2018071107A1

公开(公告)日：2018-04-19

申请号：PCT/US2017/049755

申请日：2017-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YUH, Jong Hak ,  CERNEA, Raul Adrian ,  LEE, Seungpil ,  LI, Yen-Lung ,  NGUYEN, Qui ,  TSENG, Tai-Yuan ,  HSU, Cynthia

IPC: G11C16/12 ,  G11C16/24

Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory 122. A bit line 302 is coupled to storage cells for a non-volatile memory element 123. A sense amplifier 306 is coupled to a bit line 302. A sense amplifier 306 includes a sense circuit 402 and a bias circuit 404. A sense circuit 402 senses an electrical property of a bit line 302 for reading data from one or more storage cells, and a bias circuit 404 applies a bias voltage to the bit line 302 for writing data to one or more storage cells. A bias circuit 404 and a sense circuit 402 comprise separate parallel electrical paths within a sense amplifier 306.

Abstract translation: 公开了用于访问非易失性存储器122的设备，系统和方法。位线302耦合到用于非易失性存储器元件123的存储单元。读出放大器306耦合到 位线302.感测放大器306包括感测电路402和偏置电路404.感测电路402感测用于从一个或多个存储单元读取数据的位线302的电特性，并且偏置电路404施加偏置 电压施加到位线302以将数据写入到一个或多个存储单元。 偏置电路404和读出电路402包括读出放大器306内的分开的并行电路径。

公开(公告)号：WO2019108298A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/053362

申请日：2018-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： NGUYEN, Hao ,  BALAKRISHNAN, Gopinath ,  SIAU, Chang ,  LEE, Seungpil

IPC: G11C7/06 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/24 ,  G11C7/02 ,  G11C7/06 ,  G11C7/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C27/005 ,  G11C2207/002

Abstract: Apparatuses, systems, and methods are disclosed for current sensing for non-volatile memory. A current to voltage conversion circuit (706) may convert a current coupled to a sense amplifier (150) to an analog voltage at a sense node (708). A voltage to digital conversion circuit (710) may convert an analog voltage at a sense node (708) to a digital signal, based on a voltage difference between the sense node (708) and a comparison node (714) during a strobe time. A bias circuit (716) may bias a comparison node (714) to a bias voltage other than a reference voltage, at least during a strobe time.