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    WEAK ERASE PRIOR TO READ
    3.
    发明申请
    WEAK ERASE PRIOR TO READ 审中-公开
    在读取前弱擦除

    公开(公告)号：WO2018004753A1

    公开(公告)日：2018-01-04

    申请号：PCT/US2017/019591

    申请日：2017-02-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： PANG, Liang ,  DONG, Yingda ,  YU, Xuehong ,  REN, Jingjian

    IPC: G11C16/34 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3459

    Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.

    Abstract translation: 公开了用于精确地感测存储器单元而不必等待在感测操作停止之后在字线上爬升的电压的技术。 字线蠕变可能导致电子陷入存储器单元的浅界面陷阱中，从而影响其阈值电压。 在一个方面中，使用弱擦除操作从存储器单元的浅界面陷阱移除（例如，解俘获）俘获的电子。 因此，减少或防止了与字线电压蠕变相关的问题。 因此，可以在不等待的情况下感测存储器单元，同时仍然提供准确的结果。 弱擦除可能是感测操作的一部分，但这不是必需的。 例如，弱擦除可以包含在读操作的开始部分，这提供了非常有效的解决方案。

    NON-VOLATILE MEMORY WITH CUSTOMIZED CONTROL OF INJECTION TYPE OF DISTURB DURING READ OPERATIONS
    4.
    发明申请
    NON-VOLATILE MEMORY WITH CUSTOMIZED CONTROL OF INJECTION TYPE OF DISTURB DURING READ OPERATIONS 审中-公开
    非易失性存储器，可在读取操作期间自定义控制注入类型的干扰

    公开(公告)号：WO2017209812A1

    公开(公告)日：2017-12-07

    申请号：PCT/US2017/018758

    申请日：2017-02-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： CHEN, Hong-Yan ,  DONG, Yingda

    IPC: G11C11/56 ,  G11C16/08 ,  G11C16/28 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C8/08 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal.

    Abstract translation: 非易失性存储器系统包括被配置为读取存储器单元的一个或多个控制电路。 编程的存储器单元的读取包括施加一个或多个电压以执行与未选中的存储器单元相关联的沟道区域的升压，允许在施加一个或多个电压的同时升高沟道区域的一部分时间，防止/中断 在选择用于验证的存储单元的位置的基础上，在施加一个或多个电压一段时间的同时施加一个或多个电压，向选择用于读取的存储单元施加比较信号，并且对所选择的存储单元执行感测操作 用于响应比较信号进行读取。

    MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES
    6.
    发明申请
    MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES 审中-公开
    多栅极或闪烁的薄膜晶体管阵列安装在垂直控制门的堆叠水平有源条中

    公开(公告)号：WO2017058347A1

    公开(公告)日：2017-04-06

    申请号：PCT/US2016/044336

    申请日：2016-07-27

    Applicant: HARARI, Eli

    Inventor： HARARI, Eli

    IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  H01L29/792

    CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays ("multi-gate NOR string arrays") are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

    Abstract translation: 多栅极NOR闪存薄膜晶体管（TFT）串阵列（“多栅极NOR串阵列”）被组织为平行于硅衬底的表面延伸的水平有源条的堆叠，每个堆叠中的TFT被控制 通过沿着活动条的堆叠的一个或两个侧壁设置的垂直的局部字线。 每个有源条带至少包括在两个共用源极或漏极层之间形成的沟道层。 有源条带的TFT中的数据存储由提供在有源条和由相邻本地字线提供的控制栅之间的电荷存储元件提供。 取决于使用活动条的一侧还是两侧，每个活动条可以提供属于一个或两个NOR字符串的TFT。

    ON DEMAND KNOCKOUT OF COARSE SENSING BASED ON DYNAMIC SOURCE BOUNCE DETECTION
    7.
    发明申请
    ON DEMAND KNOCKOUT OF COARSE SENSING BASED ON DYNAMIC SOURCE BOUNCE DETECTION 审中-公开
    基于动态源检测的干扰检测需求分析

    公开(公告)号：WO2017048414A1

    公开(公告)日：2017-03-23

    申请号：PCT/US2016/046173

    申请日：2016-08-09

    Applicant: INTEL CORPORATION ,  KAVALIPURAPU, Kalyan C. ,  PARK, Jae-Kwan ,  YU, Erwin E. ,  PICCARDI, Michele

    Inventor： KAVALIPURAPU, Kalyan C. ,  PARK, Jae-Kwan ,  YU, Erwin E. ,  PICCARDI, Michele

    IPC: G11C16/34 ,  G11C16/04 ,  G06F11/10

    CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3454

    Abstract: Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.

    Abstract translation: 系统，装置和方法可以提供用于确定与一个或多个存储器单元相关联的源极线上的反弹电压的大小，并且如果反弹电压的大小超过阈值，则进行粗略级程序验证， 一个或多个存储器单元的级别程序验证。 此外，如果反弹电压的大小不超过阈值，则只能执行一个或多个存储器单元的精细级程序验证。 在一个示例中，如果反弹电压的幅度不超过阈值，则旁路粗略级程序验证。

    MULTIPLE BLOCKS PER STRING IN 3D NAND MEMORY
    8.
    发明申请
    MULTIPLE BLOCKS PER STRING IN 3D NAND MEMORY 审中-公开
    3D NAND存储器中每个字节的多个块

    公开(公告)号：WO2017044220A1

    公开(公告)日：2017-03-16

    申请号：PCT/US2016/045766

    申请日：2016-08-05

    Applicant: INTEL CORPORATION

    Inventor： GODA, Akira ,  WOLSTENHOLME, Graham Richard ,  TANAKA, Tomoharu

    IPC: G11C16/08 ,  G11C16/04 ,  H01L27/115

    CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3495

    Abstract: Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to different memory blocks (e.g., multiple memory blocks per string). For example, a first set of memory cells of a string may be included in a first memory block, and a second set of memory cells of the string may be included in a second memory block. The memory device may include separator wordlines disposed between wordlines associated with the first memory block and wordlines associated with the second memory block. The separator wordlines may receive different bias voltages during various operations of the memory device. Additionally, a wordline biasing scheme may be selected to program the first memory block based on whether the second memory block is programmed. Other embodiments may be described and/or claimed.

    Abstract translation: 实施例描述了包括具有多个存储单元串的三维（3D）存储器阵列的设备的技术和配置，其中单独的串可具有对应于不同存储器块（例如，每个串的多个存储器块）的存储器单元。 例如，字符串的第一组存储器单元可以被包括在第一存储器块中，并且串的第二组存储器单元可以被包括在第二存储器块中。 存储器件可以包括设置在与第一存储器块相关联的字线和与第二存储器块相关联的字线之间的分离器字线。 分离器字线可以在存储器件的各种操作期间接收不同的偏置电压。 另外，可以选择字线偏移方案来基于第二存储器块是否被编程来对第一存储器块进行编程。 可以描述和/或要求保护其他实施例。

    PROXY WORDLINE STRESS FOR READ DISTURB DETECTION
    9.
    发明申请
    PROXY WORDLINE STRESS FOR READ DISTURB DETECTION 审中-公开
    用于读取干扰检测的代码字线应力

    公开(公告)号：WO2017044167A1

    公开(公告)日：2017-03-16

    申请号：PCT/US2016/036931

    申请日：2016-06-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： REUSSWIG, Philip ,  SINGIDI, Harish ,  RAGHU, Deepak ,  DUSIJA, Gautam ,  KOH, Pao-ling ,  AVILA, Chris

    IPC: G11C16/34

    CPC classification number: G11C16/3431 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422 ,  G11C16/349 ,  G11C29/52

    Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

    Abstract translation: 提供了方法和系统，其中非易失性固态存储器可以包括耦合到选定字线的选定存储器单元和耦合到代理字线的代理存储器单元。 所选择的存储器单元可以不与代理存储器单元相邻并且被选择用于读取操作。 当从所选择的存储单元读取数据时，读取代理电压可被施加到代理字线。 可以基于存储在代理存储单元中的预定值和从代理存储单元读取的值之间的差来确定读取干扰。

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