公开(公告)号：WO2018106302A1

公开(公告)日：2018-06-14

申请号：PCT/US2017/050866

申请日：2017-09-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： MASUDUZZAMAN, Muhammad ,  DUTTA, Deepanshu ,  YUH, Jong

IPC: G11C16/10 ,  G11C16/30 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3495

Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

公开(公告)号：WO2017112817A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/068128

申请日：2016-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YANG, Xiang ,  TSENG, Huai-Yuan ,  MIAO, Xiaochang ,  DUTTA, Deepanshu

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5648

Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

Abstract translation: 用于在使用NAND串执行感测操作之后或在感测操作期间减少NAND串内的残余电子的系统和方法。 可以执行中间编程序列，其中在对NAND串的中间的存储器单元晶体管进行编程并且在对NAND串的漏极侧末端和/或源极进行编程和验证其他存储器单元晶体管之前进行编程验证 NAND串的末端。 在一个示例中，对于具有与从NAND串的源极端到NAND串的漏极端的字线WL0到WL31对应的32个存储器单元晶体管的NAND串，与字线WL16对应的存储器单元晶体管 可以在对与字线WL15和WL17对应的存储器单元晶体管进行编程之前被编程和编程验证。

公开(公告)号：WO2017091338A1

公开(公告)日：2017-06-01

申请号：PCT/US2016/060457

申请日：2016-11-04

Applicant: HARARI, Eli

Inventor： HARARI, Eli

IPC: G11C7/18 ,  H01L21/8242 ,  G11C11/409

CPC classification number: H01L27/11578 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/11551

Abstract: A memory structure, includes a plurality of thin film transistors associated with each of a plurality of active columns, which are organized into one or more vertical NOR strings comprising (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form the plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions.

Abstract translation: 存储器结构包括与多个有源列中的每一个相关联的多个薄膜晶体管，所述多个薄膜晶体管被组织成一个或多个垂直NOR列，所述一个或多个垂直NOR列包括：（a）形成在 半导体衬底，每个有源列从所述衬底垂直延伸，其中所述有源列布置成在平行于所述半导体衬底的平坦表面的第二和第三方向上延伸的二维阵列; （b）提供在每个活性柱的一个或多个表面上的电荷俘获材料; 和（c）各自沿着第三方向纵向延伸的导体。 有源柱，电荷俘获材料和导体一起形成多个薄膜晶体管，每个薄膜晶体管由导体中的一个形成，有源柱的轻掺杂区域的一部分，电荷俘获材料 在轻掺杂区的该部分和导体之间以及第一和第二重掺杂区之间

公开(公告)号：WO2017019189A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/037004

申请日：2016-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： BEN-RUBI, Refael ,  SHLICK, Mark ,  COHEN, Moshe

IPC: G11C8/10 ,  G11C11/56 ,  G11C29/52 ,  G11C29/44

CPC classification number: G11C29/04 ,  G11C7/00 ,  G11C8/10 ,  G11C11/5642 ,  G11C17/16 ,  G11C29/18 ,  G11C29/26 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A data storage device includes a memory including a plurality of storage elements configured to store data. The plurality of storage elements includes a first group of storage elements and a second group of storage elements. The data storage device further includes a selection module configured to retrieve first bit line defect information affecting the first group of storage elements and to retrieve second bit line defect information affecting the second group of storage elements.

Abstract translation: 数据存储装置包括存储器，其包括被配置为存储数据的多个存储元件。 多个存储元件包括第一组存储元件和第二组存储元件。 数据存储设备还包括选择模块，其被配置为检索影响第一组存储元件的第一位线缺陷信息，并且检索影响第二组存储元件的第二位线缺陷信息。

公开(公告)号：WO2016053558A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/048001

申请日：2015-09-01

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： YUAN, Jiahui ,  DONG, Yingda ,  KWONG, Charles ,  CHEN, Hong-Yan ,  PANG, Liang

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/52

Abstract: A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. The read operation occurs in connection with a programming operation which avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading memory cells on a selected word line, WLn, memory cells on WLn-1 are read. The read operation for WLn uses multiple read voltages - one for each data state on WLn-1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.

Abstract translation: 当识别擦除状态和最低编程数据状态时，读取操作补偿程序干扰，其中程序干扰是公共电荷俘获层上相邻的预先编程的存储器单元的数据状态的函数。 读操作与编程操作相关，通过使用不对称通过电压避免编程数据状态的程序干扰。 在读取所选字线上的存储单元之前，WLn读取WLn-1上的存储单元。 WLn的读取操作使用多个读取电压 - 一个用于WLn-1上的每个数据状态，并且根据相邻存储器单元的数据状态选择一个读取结果。 其他读取操作使用独立于相邻存储器单元的数据状态的读取电压来区分每对相邻的编程数据状态。

公开(公告)号：WO2016043961A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/047800

申请日：2015-08-31

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： RAY, Biswajit ,  DUNGA, Mohan ,  CHEN, Chagyuan

IPC: G11C7/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

Abstract: Methods for reducing cross-temperature dependent word line failures using a temperature dependent sensing scheme during a sensing operation are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time, source line voltage, or bit line voltage) may be set based on a temperature of the memory cells during sensing and a word line location of the memory cells to be sensed. In one example, the memory array may comprise a NAND memory array that includes a NAND string and the sensing time for sensing a memory cell of the NAND string and the source line voltage applied to a source line connected to a source end of the NAND string may be set based on the temperature of the memory cells during sensing and the word line location of the memory cells to be sensed.

Abstract translation: 描述了在感测操作期间使用温度依赖感测方案来降低依赖于温度的字线故障的方法。 在一些实施例中，在读取操作期间，可以基于感测期间存储器单元的温度来设置施加到存储器阵列内的存储器单元的感测条件（例如，感测时间，源极线电压或位线电压） 要感测的存储单元的字线位置。 在一个示例中，存储器阵列可以包括NAND存储器阵列，其包括NAND串和用于感测NAND串的存储单元的感测时间，以及施加到连接到NAND串的源极端的源极线的源极线电压 可以基于感测期间的存储器单元的温度和要感测的存储器单元的字线位置来设置。

公开(公告)号：WO2016043959A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/047627

申请日：2015-08-30

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： RAY, Biswajit ,  DOGAN, Abuzer ,  CHEN, Changyuan

IPC: G11C7/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

Abstract: Methods for reducing cross-temperature threshold voltage distribution widening by applying a temperature dependent sensing scheme during read operations are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array may be set and/or adjusted based on a temperature of the memory cells during the read operation, a previous temperature of the memory cells when the memory cells were programmed, and the programmed states of neighboring memory cells. In some cases, the sensing time for sensing a memory cell of a NAND string and the source voltage applied to a source line connected to the NAND string may be set based on the temperature of the memory cells during sensing and the previous temperature of the memory cells when the memory cells were programmed.

Abstract translation: 描述了在读取操作期间通过应用温度依赖感测方案来降低交叉温度阈值电压分布加宽的方法。 在一些实施例中，在读取操作期间，可以基于读取操作期间存储器单元的温度，存储器单元的先前温度，存储器单元的先前温度，设置和/或调整应用于存储器阵列内的存储器单元的感测条件 单元被编程，以及相邻存储单元的编程状态。 在一些情况下，用于感测NAND串的存储单元的感测时间和施加到连接到NAND串的源极线的源极电压可以基于感测期间存储器单元的温度和存储器的先前温度来设置 当存储器单元被编程时的单元。

公开(公告)号：WO2016038743A1

公开(公告)日：2016-03-17

申请号：PCT/JP2014/074297

申请日：2014-09-12

Applicant: 株式会社 東芝

Inventor： 鎌田　義彦 ,  田畑　浩司

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C7/08 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642

Abstract: 　Ｎビットのデータを保持可能なメモリセルが配置されたメモリセルアレイと、閾値分布の情報を保持可能な第１ラッチ（SEN）と、書き込みデータを保持する第２ラッチ（SDL）と、前記２ビットデータの下位情報を可能とする第３ラッチ（LDL）を有し、前記メモリセルに第１～第４電圧を供給し、この第１～第４電圧を用いて前記データの書き込みをするセンスアンプとを具備し、前記センスアンプは、前記第２ラッチ、及び前記第３ラッチが保持する情報に基づいて前記第１～第３電圧（VSS、VDD、VQPWL）を前記メモリセルに供給し、次いで前記第１ラッチが保持する前記情報を前記第２ラッチへと転送したことで得られる結果に基づき、前記第４電圧（VQPWH）、又は前記第１電圧（VSS）を前記メモリセルに供給する。

Abstract translation: 该非易失性半导体存储装置设置有存储单元阵列，其中存储单元，每个存储单元能够保持N位数据; 以及读出放大器，其具有能够保持阈值分布信息的第一锁存电路（SEN），能够保持写入数据的第二锁存电路（SDL）以及能够保持低位数的第三锁存电路（LDL） 2位数据的信息，并且向存储单元提供第一至第四电压，所述读出放大器使用第一至第四电压写入数据。 读出放大器基于通过第二锁存电路和第三锁存电路保持的信息向存储器单元提供第一至第三电压（VSS，VDD，VQPWL），然后基于通过转移获得的结果 通过第一锁存电路保存到第二锁存电路的信息，读出放大器将第四电压（VQPWH）或第一电压（VSS）提供给存储器单元。

公开(公告)号：WO2015094799A3

公开(公告)日：2015-08-13

申请号：PCT/US2014069236

申请日：2014-12-09

Applicant: SANDISK TECHNOLOGIES INC

Inventor： ALROD IDAN ,  SHARON ERAN ,  MEKHANIK EVGENY

IPC: G11C11/56 ,  G11C16/26

CPC classification number: G11C29/50004 ,  G06F11/076 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/121 ,  G06F2212/7209 ,  G11C11/5642 ,  G11C16/26 ,  G11C2029/5004

Abstract: A data storage device includes a controller coupled to a non-volatile memory. The non-volatile memory is configured to store multiple tags that include a first tag and a second tag. The controller is configured to determine one or more candidate values associated with a candidate tag. The one or more candidate values may be determined based on an operation applied to the first tag and the second tag. The controller is further be configured to cause the non-volatile memory to remove the first tag or the second tag from the multiple tags.

Abstract translation: 数据存储设备包括耦合到非易失性存储器的控制器。 非易失性存储器被配置为存储包括第一标签和第二标签的多个标签。 控制器被配置为确定与候选标签相关联的一个或多个候选值。 可以基于应用于第一标签和第二标签的操作来确定一个或多个候选值。 控制器还被配置为使得非易失性存储器从多个标签中移除第一标签或第二标签。

公开(公告)号：WO2015053919A4

公开(公告)日：2015-06-18

申请号：PCT/US2014056403

申请日：2014-09-18

Applicant: SANDISK TECHNOLOGIES INC

Inventor： DUNGA MOHAN V ,  HIGASHITANI MASAAKI

IPC: G11C16/34 ,  G11C5/14 ,  G11C7/12 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3454 ,  G11C7/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459

Abstract: In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.

Abstract translation: 在一块非易失性存储器中，位线电流随位线电压而增加。 对于电流感测存储器系统，在感测操作期间的平均位线电流仅需要超过某个阈值量以产生正确的结果。 对于在块中编程的第一个字线，与其连接的存储器单元在验证操作期间看到相对低的位线电阻。 在所公开的技术中，对具有较低验证位线电压的这些第一编程字线执行验证操作，以便减少多余的位线电流并节省功率。 在读取操作期间，该方案可以使连接到较低字线的存储单元的阈值电压更低。 为了补偿这种效果，公开了各种方案。