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公开(公告)号：WO2007092438A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/003139
申请日：2007-02-07
Applicant: INFINEON TECHNOLOGIES AG , GRAI, Tim , BREWERTON, Simon , LETEINTURIER, Patrick
Inventor： GRAI, Tim , BREWERTON, Simon , LETEINTURIER, Patrick
CPC classification number: F02D35/021 , F02D35/027 , F02D2041/1432 , F02D2041/288 , F02P5/152 , G01L23/225
Abstract: One embodiment of the invention provides a detection system. The detection system includes an analog to digital converter that converts one or more analog vibration signals into one or more digital samples, a filter that analyzes at least a portion of the one or more, digital samples and identifies energy values across a range of frequencies, a frequency selector that selects a subset of the frequencies for analysis according to one or more operational characteristics, and an analyzer that analyzes the subset of frequencies along with threshold values to identify one or more results.
Abstract translation: 本发明的一个实施例提供一种检测系统。 检测系统包括将一个或多个模拟振动信号转换为一个或多个数字样本的模数转换器，分析一个或多个数字样本的至少一部分并识别频率范围内的能量值的滤波器， 频率选择器，其根据一个或多个操作特征选择用于分析的频率子集;以及分析器，其分析频率子集以及阈值以识别一个或多个结果。
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公开(公告)号：WO2020139458A2
公开(公告)日：2020-07-02
申请号：PCT/US2019/058792
申请日：2019-10-30
Applicant: INTEL CORPORATION
Inventor： HENZLER, Stephan , HERBISON, David , NEBOROVSKI, Emil , PIOREK, Thomas , WANG, Yifan , WENSKE, Holger , WERTH, Tobias
Abstract: Systems, methods, and circuitries for regulating voltage supplied to a power amplifier are disclosed. A buck-boost control system is configured to control a buck-boost converter to operate in either a buck mode or a boost mode. The system includes compensator circuitry configured to determine a target current based on a difference between a target voltage and a regulated output voltage of the buck-boost converter and determine a tolerance current that, with the target current, defines a range of expected coil current. Based on the difference between the target voltage and the regulated output voltage, a charge control signal or a discharge control signal is generated for the converter to cause the coil current to approach the target current. Mode control circuitry is configured to switch the buck-boost converter to the other operating mode when the coil current reaches the tolerance current.
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公开(公告)号：WO2020102481A1
公开(公告)日：2020-05-22
申请号：PCT/US2019/061378
申请日：2019-11-14
Applicant: INTEL CORPORATION
Inventor： ZHANG, Yushu , DAVYDOV, Alexei , XIONG, Gang , HE, Hong , LEE, Daewon
IPC: H04B7/0408 , H04B7/06 , H04B17/373
Abstract: An apparatus configured to be employed in a gNodeB associated with a new radio (NR) communication system is disclosed. The apparatus comprises one or more processors configured to determine a timing relation associated with a set of downlink (DL) beams associated with the gNodeB to be utilized for DL transmission. In some embodiments, the one or more processors is further configured to configure a gap to be applied to a set of DL signals respectively associated with the set of DL beams during DL transmission, based on the determined timing relation associated with the set of DL beams, In some embodiments, the configured gap enables to reduce an interference between the set of DL signals, when beam switching between the set of DL beams.
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公开(公告)号：WO2020096852A1
公开(公告)日：2020-05-14
申请号：PCT/US2019/059070
申请日：2019-10-31
Applicant: INTEL CORPORATION
Inventor： WANG, Guotong , ZHANG, Yushu , DAVYDOV, Alexei , XIONG, Gang
IPC: H04L5/00 , H04B17/373 , H04W72/12
Abstract: An apparatus configured to be employed in a user equipment (UE) associated with a new radio (NR) communication system is disclosed. The apparatus comprises one or more processors configured to process a physical downlink shared channel (PDSCH) scheduling signal, received from a gNodeB associated therewith, wherein the PDSCH scheduling signal is configured to schedule a transmission of PDSCH. In some embodiments, the PDSCH scheduling signal comprises a transmission configuration indicator (TCI) state indicative of a channel state information reference signal (CSI-RS) resource that is triggered aperiodically. In some embodiments, the apparatus is further configured to determine a receive (Rx) beam to be utilized for the reception of the scheduled PDSCH transmission, that forms a PDSCH Rx beam, based on the indicated CSI-RS resource.
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95.发明申请
公开(公告)号：WO2020091937A1
公开(公告)日：2020-05-07
申请号：PCT/US2019/053972
申请日：2019-10-01
Applicant: INTEL CORPORATION
Inventor： DASGUPTA, Kaushik , YU, Chuanzhao , THAKKAR, Chintan , DANESHGAR, Saeid , YOON, Hyun , LI, Xi , CHAKRABARTI, Anandaroop , SHOPOV, Stefan
Abstract: An on-chip transformer circuit (200) is disclosed. The on-chip transformer circuit comprises a primary winding circuit (202) comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit (204) comprising at least one turn of a secondary conductive winding arranged as a second INI- sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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Patent Agency Ranking
公开(公告)号：WO2020068340A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/048496
申请日：2019-08-28
Applicant: INTEL CORPORATION
Inventor： DAVIS, Brandon , BALAKRISHNAN, Aishwarya
Abstract: A polyphase filter operates to provide capacitive compensation to drive a multiphase network for generating quadrature signals. The polyphase filter (220) can include a capacitive compensation mechanism (340,350) at internal nodes. The capacitive compensation mechanism includes a first phase lag circuit (340) between a first internal node (XI) and a second internal node (X2) and a second phase lag circuit (350) coupled between a third internal node (X3) and a fourth internal node (X4). The first internal node is coupled to the second internal node via a first inductor (320) coupled to a first resistor (Rp1), the second internal node is coupled to the third internal node via a second inductor (322) coupled to a second resistor (Rp2), the third internal node is coupled to the fourth internal node via a third inductor (324) coupled to a third resistor (Rp3), and the fourth internal node is coupled to the first internal node via a fourth inductor (326) coupled to a fourth resistor (Rp4).
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公开(公告)号：WO2020055510A1
公开(公告)日：2020-03-19
申请号：PCT/US2019/043213
申请日：2019-07-24
Applicant: INTEL CORPORATION
Inventor： KUNDU, Somnath , PELLERANO, Stefano , AGRAWAL, Abhishek
Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.
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公开(公告)号：WO2020047024A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/048454
申请日：2019-08-28
Applicant: INTEL CORPORATION
Inventor： MIAO, Honglei
Abstract: An apparatus configured to be employed in a gNodeB associated with a new radio (NR) system is disclosed. The apparatus comprises one or more processors configured to configure one or more sidelink sounding reference signals (SRS), for one or more user equipments (UEs) associated with the gNodeB, to be utilized by the one or more UEs for transmission or reception, or both, over sidelink. The one or more processors is further configured to generate one or more sidelink SRS configuration signals to be provided, respectively, to the one or more UEs, wherein each sidelink SRS configuration signal comprises sidelink SRS configuration information on the one or more sidelink SRS configured for a respective UE. The apparatus further comprises a radio frequency (RF) interface, configured to provide, to a radio frequency (RF) circuitry, the one or more sidelink SRS configuration signals, for subsequent transmission to the one or more UEs, respectively.
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99.发明申请
公开(公告)号：WO2020033620A1
公开(公告)日：2020-02-13
申请号：PCT/US2019/045614
申请日：2019-08-08
Applicant: INTEL CORPORATION
Inventor： MOROZOV, Gregory V. , YE, Qiaoyang , CHATTERJEE, Debdeep
Abstract: An apparatus configured to be employed in an eNodeB associated with a long term evolution (LTE) communication system is disclosed. The apparatus comprises one or more processors configured to generate a set of repeated transmissions of a channel state information reference signal (CSI-RS), forming a repeated CSI-RS, to be provided to a user equipment (UE) in a set of CSI-RS subframes, respectively associated with an LTE frame structure, in order to enable the UE to determine channel state information (CSI) based on the repeated CSI-RS. In some embodiments, the apparatus further comprises a radio frequency (RF) interface, configured to provide, to a radio frequency (RF) circuitry, the repeated CSI-RS, for subsequent transmission to the UE in the set of CSI-RS subframes.
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100.发明申请
公开(公告)号：WO2019190542A1
公开(公告)日：2019-10-03
申请号：PCT/US2018/025313
申请日：2018-03-30
Applicant: INTEL IP CORPORATION
Inventor： FAERBER, Michael , ROTH, Kilian , SARAVANAN, Visvesh , GOMES BALTAR, Leonardo
Abstract: Methods and architectures are described to allow concurrent operation of two separate, non-synchronized, radio systems utilizing closely spaced frequency bands, such as IEEE 802.11p and LTE-V2X, or NR-V2X vehicular communications systems, with a common antenna. A full duplex-"like" active interference cancellation process may be employed that includes self-interference cancellation in the RF domain, in the analog domain and the digital baseband domain to reduce complexities and costs of stringent antenna isolation, otherwise required, for a simultaneous TX and RX mode of operation and concurrent RX mode of operation in closely spaced frequency resources.
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