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    HIGH PARALLELISM DEPENDENCY PATTERN FOR GPU BASED DEBLOCK
    91.
    发明申请
    HIGH PARALLELISM DEPENDENCY PATTERN FOR GPU BASED DEBLOCK 审中-公开
    基于GPU的DEBLOCK的高并发性依赖性模式

    公开(公告)号：WO2016093978A1

    公开(公告)日：2016-06-16

    申请号：PCT/US2015/058573

    申请日：2015-11-02

    Applicant: INTEL CORPORATION

    Inventor： WU, Haihua ,  GOULD, Julia A.

    IPC: H04N19/44 ,  H04N19/176

    CPC classification number: H04N19/436 ,  H04N19/117 ,  H04N19/82 ,  H04N19/86 ,  H04N19/865

    Abstract: A thread dependency scheme may significantly reduce the dependency penalty and improve the parallelism efficiency in some embodiments in video compression techniques with relatively high dependencies, such as VP9. One fundamental feature is to split an individual large kernel into multiple, less dependent, smaller kernels, thereby significantly increasing the number of software threads that can potentially run in parallel. Another feature is to define the larger number of thread dependencies (superset of all the dependency candidates for each thread), with the specific thread's spatial position and associated context, and mask out some of the unnecessary thread dependencies.

    Abstract translation: 线程依赖方案可以显着地减少依赖性损失并且在一些实施例中提高具有较高依赖性的视频压缩技术（例如VP9）中的并行性效率。 一个基本特征是将单个大型内核分解成多个较少依赖的较小内核，从而显着增加可能并行运行的软件线程数。 另一个特点是定义更多数量的线程依赖性（每个线程的所有依赖候选项的超集），以及特定线程的空间位置和关联的上下文，并且屏蔽一些不必要的线程依赖关系。

    COMPRESSING THE SIZE OF COLOR LOOKUP TABLES
    92.
    发明申请
    COMPRESSING THE SIZE OF COLOR LOOKUP TABLES 审中-公开
    压缩颜色查看表的大小

    公开(公告)号：WO2016085589A1

    公开(公告)日：2016-06-02

    申请号：PCT/US2015/056675

    申请日：2015-10-21

    Applicant: INTEL CORPORATION

    Inventor： BHATTACHARJEE, Susanta ,  KP, Sameer

    IPC: H04N19/60 ,  H04N19/00

    CPC classification number: G09G5/06 ,  G09G5/363 ,  G09G2340/06

    Abstract: By converting a first color space to a second color space, using a two-dimensional lookup table in said second color space, and converting from said second color space to said first color space, it may be possible to use one or more two-dimensional lookup tables (LUTs) to do a task conventionally handled by three-dimensional lookup tables. This may reduce storage requirements and memory bandwidth requirements in some embodiments. In general a color pixel with N color components can be processed with n number of M dimensional LUT where M

    Abstract translation: 通过将第一颜色空间转换为第二颜色空间，使用所述第二颜色空间中的二维查找表，以及从所述第二颜色空间转换为所述第一颜色空间，可以使用一个或多个二维 查找表（LUT）来执行通常由三维查找表处理的任务。 这在一些实施例中可以减少存储要求和存储器带宽要求。 通常，可以用n个M维LUT来处理具有N个颜色分量的彩色像素，其中M

    POWER OPTIMIZATION WITH DYNAMIC FRAME RATE SUPPORT
    93.
    发明申请
    POWER OPTIMIZATION WITH DYNAMIC FRAME RATE SUPPORT 审中-公开
    动力优化与动态帧速率支持

    公开(公告)号：WO2015200631A1

    公开(公告)日：2015-12-30

    申请号：PCT/US2015/037687

    申请日：2015-06-25

    Applicant: INTEL CORPORATION

    Inventor： KWA, Seh W. ,  ANSARI, Nausheen ,  AVADHANAM, Satyanarayana

    IPC: G09G3/20 ,  H04N7/01

    CPC classification number: G06T1/20 ,  G06K9/00624 ,  G09G5/00 ,  G09G5/18 ,  G09G2330/022 ,  G09G2340/0435

    Abstract: A frame of pixel data may be burst at a higher frame rate to create a lower effective refresh rate when the actual image update rate is lower than the frame rate. This results in the ability to power manage the transmit portion of the display engine and the receive portion of the panel electronics, while reducing display initiated repetitive memory traffic to conserve power.

    Abstract translation: 当实际图像更新速率低于帧速率时，像素数据的帧可以以更高的帧速率突发以产生较低的有效刷新率。 这导致能够管理显示引擎的发送部分和面板电子装置的接收部分，同时减少显示器启动的重复存储器流量以节省功率。

    VULNERABILITY ESTIMATION FOR CACHE MEMORY
    94.
    发明申请
    VULNERABILITY ESTIMATION FOR CACHE MEMORY 审中-公开
    缓存记忆的易损性估计

    公开(公告)号：WO2014142852A1

    公开(公告)日：2014-09-18

    申请号：PCT/US2013/031038

    申请日：2013-03-13

    Applicant: INTEL CORPORATION

    Inventor： CASADO, Javier Carretero ,  VERA, Xavier ,  RAMIREZ, Tanausu ,  SANCHEZ, Daniel ,  ABELLANAS, Enric Herrero ,  AXELOS, Nicholas

    IPC: G06F11/00 ,  G06F12/08 ,  G06F13/14

    CPC classification number: G06F11/3409 ,  G06F11/3471 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.

    Abstract translation: 确定高速缓存存储器的脆弱性的方法包括将第一计数器与高速缓存元件相关联并周期性地增加第一计数器。 当消耗高速缓存元件中的数据的读取或其他访问时，累积第一计数器的当前值。 当发生修改高速缓存元件中的数据的写入或其他高速缓存访​​问时，第一个计数器被复位。 在评估期结束时，总计数器中的值近似于所消耗数据易受攻击的时钟周期数。 将此值除以时钟周期数可以逼近此缓存元素的漏洞。 所有高速缓存元素的子集的漏洞可以被测量和推断，以获得整体高速缓冲存储器的漏洞的估计。

    STOCHASTIC DEPTH BUFFER COMPRESSION USING GENERALIZED PLANE ENCODING
    95.
    发明申请
    STOCHASTIC DEPTH BUFFER COMPRESSION USING GENERALIZED PLANE ENCODING 审中-公开
    使用广义平面编码的STOCHASTIC深度缓冲器压缩

    公开(公告)号：WO2014051793A1

    公开(公告)日：2014-04-03

    申请号：PCT/US2013/048034

    申请日：2013-06-27

    Applicant: INTEL CORPORATION

    Inventor： ANDERSSON, Magnus ,  MUNKBERG, Carl. J. ,  AKENINE-MÖLLER, Thomas G. ,  HASSELGREN, Jon N.

    IPC: H04N13/00 ,  G06T5/00

    CPC classification number: G06T11/40 ,  G06T9/00 ,  G06T15/40

    Abstract: Unlike a static primitive, where the depth function is planar, the depth function for a moving and defocused triangle is a rational function in time and the lens parameters. Compact depth functions can be used to design an efficient depth buffer compressor/decompressor, which significantly lowers total depth buffer bandwidth usage. In addition, this compressor/decompressor is substantially simpler in the number of operations needed to execute, which makes it more amenable for hardware implementation than previous methods.

    Abstract translation: 与静态原语不同，其中深度函数是平面的，移动和散焦三角形的深度函数是时间上的理性函数和透镜参数。 紧凑的深度功能可用于设计一个高效的深度缓冲压缩/解压缩器，显着降低了总深度缓冲带宽的使用。 此外，该压缩器/解压缩器在执行所需的操作数量上基本上更简单，这使得它比以前的方法更适合硬件实现。

    PROTOCOL FOR COMMUNICATIONS BETWEEN PLATFORMS AND IMAGE DEVICES
    96.
    发明申请
    PROTOCOL FOR COMMUNICATIONS BETWEEN PLATFORMS AND IMAGE DEVICES 审中-公开
    平台和图像设备之间的通信协议

    公开(公告)号：WO2014039457A1

    公开(公告)日：2014-03-13

    申请号：PCT/US2013/057891

    申请日：2013-09-03

    Applicant: INTEL CORPORATION

    Inventor： KRIG, Scott A.

    IPC: G06F13/42

    CPC classification number: H04N1/32117 ,  G06K9/00221 ,  G06K9/00335 ,  H04N1/00129 ,  H04N1/00251 ,  H04N1/00278 ,  H04N1/00307 ,  H04N1/44 ,  H04N1/6058 ,  H04N5/23203 ,  H04N2201/0055 ,  H04N2201/0074

    Abstract: In accordance with some embodiments, a protocol permits communications between platforms and image devices. This allows, for example, the platform to specify particular types of information that the platform may want, the format of information the platform may prefer, and other information that may reduce the amount of processing in the platform. For example, conventionally, in gesture recognition software, the platform receives an ongoing stream of video to be parsed, searched and processed in order to identify gestures. This may consume communications bandwidth between platforms and imaging devices, particularly in cases where wireless communications or other bandwidth limited communications may be involved.

    Abstract translation: 根据一些实施例，协议允许平台和图像设备之间的通信。 这允许例如平台来指定平台可能需要的特定类型的信息，平台可能喜欢的信息的格式以及可以减少平台中的处理量的其他信息。 例如，传统上，在手势识别软件中，平台接收待解析，搜索和处理的正在进行的视频流，以便识别手势。 这可能消耗平台和成像设备之间的通信带宽，特别是在可能涉及无线通信或其他带宽限制的通信的情况下。

    TWO BINS PER CLOCK CABAC DECODING
    98.
    发明申请
    TWO BINS PER CLOCK CABAC DECODING 审中-公开
    每双时钟CABAC解码

    公开(公告)号：WO2013148739A1

    公开(公告)日：2013-10-03

    申请号：PCT/US2013/033951

    申请日：2013-03-26

    Applicant: INTEL CORPORATION

    Inventor： CHAN, Hiu-Fai R. ,  WONG, Samuel ,  CHENG, Scott W. ,  QURASHI, Mohmad I.

    IPC: H04N7/26

    CPC classification number: H04N19/90 ,  H04N19/91

    Abstract: CABAC coefficient decoding may be increased to two bins per clock. Since coefficients comprise most of the bitstream, this improvement almost doubles the CABAC decoding for a low quantization parameter bitstream (with lots of coefficients).

    Abstract translation: CABAC系数解码可以每个时钟增加到两个箱。 由于系数包括大多数比特流，所以这种改进对于低量化参数比特流（具有大量系数）几乎使CABAC解码加倍。

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