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    A PIXEL CELL VOLTAGE CONTROL CIRCUIT
    91.
    发明申请
    A PIXEL CELL VOLTAGE CONTROL CIRCUIT 审中-公开
    像素电池电压控制电路

    公开(公告)号：WO2005104071A1

    公开(公告)日：2005-11-03

    申请号：PCT/US2003/041386

    申请日：2003-12-23

    Applicant: eLCOS MICRODISPLAY TECHNOLOGY, INC.

    Inventor： HUDSON, Edwin, Lyle

    IPC: G09G3/18

    CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0857 ,  G09G2320/0204 ,  G09G2320/0247 ,  H04N9/312

    Abstract: A pixel display configuration by providing a voltage controller (320) in each pixel control circuit (205) controlling the voltage inputted to the pixel electrodes (150). The controller (320) includes a function of multiplexing the volage input to the pixel electrode (150). The controller (320) having a delay element (310) connnected to the first and second swithcing stages for delaying a turning on of one stage after a turning off of another stage with sufficient delay for loading a predefined set of display data for preventing turning one of both the first and second switching stages. The rate of DC balancing can be increased to one KHZ and higher to mitigate the possiblity of DC offset effects and image sticking problems caused by slow DC balancing rates.

    Abstract translation: 通过在每个像素控制电路（205）中设置电压控制器（320）来控制输入到像素电极（150）的电压的像素显示配置。 控制器（320）包括将输入信号复用到像素电极（150）的功能。 控制器（320）具有连接到第一和第二切换级的延迟元件（310），用于在足够的延迟关闭另一级之后延迟一级的接通，用于加载预定义的一组显示数据以防止转动一个 的第一和第二开关级。 DC平衡的速率可以提高到一个KHZ或更高，以减轻DC偏移效应的可能性和由直流平衡速率慢的图像粘附问题。

    IN-PIXEL MEMORY FOR DISPLAY DEVICES
    93.
    发明申请
    IN-PIXEL MEMORY FOR DISPLAY DEVICES 审中-公开
    用于显示设备的像素内存

    公开(公告)号：WO2003081599A1

    公开(公告)日：2003-10-02

    申请号：PCT/IB2003/000589

    申请日：2003-02-17

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  VAN DER ZAAG, Pieter, J. ,  EDWARDS, Martin, J. ,  LENSSEN, Kars-Michiel, H.

    Inventor： VAN DER ZAAG, Pieter, J. ,  EDWARDS, Martin, J. ,  LENSSEN, Kars-Michiel, H.

    IPC: G11C11/15

    CPC classification number: G09G3/20 ,  G09G2300/0857 ,  G11C11/14 ,  G11C11/16

    Abstract: Magnetoresistive random access memory (MRAM) is used to provide in-pixel memory circuits for display devices. A memory circuit (25) comprises two MRAMs (60, 62), each coupled to a respective input of a flip-flop circuit (64). A display device (1) is provided comprising a plurality of pixels (20) each associated with a memory circuit (25). A bit line (45) passes over and contacts a first MRAM (60) in a first direction and a second MRAM (62) in a second direction, the first and second directions being substantially opposite to each other. This provides opposite resistance states in the two MRAMs (60, 62). The bit line (45) does not pass over a word line (43), thereby avoiding or reducing overlap capacitance losses. The word line (43) is formed during a same masking stage as a gate line (44). The bit line (45) is formed during a same masking stage as a column line (54).

    Abstract translation: 磁阻随机存取存储器（MRAM）用于为显示设备提供像素内存电路。 存储器电路（25）包括两个MRAM（60,62），每个MRAM耦合到触发器电路（64）的相应输入端。 提供一种显示装置（1），其包括与存储电路（25）相关联的多个像素（20）。 位线（45）在第一方向上经过第一MRAM（60）并且在第二方向上接触第一MRAM（60），第二和第二方向基本上彼此相对。 这在两个MRAM（60,62）中提供相反的电阻状态。 位线（45）不通过字线（43），从而避免或减少重叠电容损耗。 字线（43）在与栅极线（44）相同的掩模阶段形成。 位线（45）在与列线（54）相同的掩模阶段形成。

    液晶表示装置およびこれを用いた携帯端末装置
    94.
    发明申请
    液晶表示装置およびこれを用いた携帯端末装置 审中-公开
    液晶显示装置和包含其的便携式终端装置

    公开(公告)号：WO2003036604A1

    公开(公告)日：2003-05-01

    申请号：PCT/JP2002/010410

    申请日：2002-10-07

    Applicant: ソニー株式会社 ,  豊澤 昇 ,  仲島 義晴

    Inventor： 豊澤 昇 ,  仲島 義晴

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G3/2011 ,  G09G3/3614 ,  G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/04 ,  G09G2320/10 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/0428

    Abstract: A liquid crystal display device which eliminates the influence of the pixel potential in write of data to a memory section and can have a large margin for the variation in the characteristics of the transistors constituting the pixel circuit and a portable terminal comprising this display device. A pixel circuit having a memory circuit 25 has two different paths: one used for write of image data from a signal line 16-i via a data write switch 24 to the memory circuit 25, and the other for read of image data held by the memory circuit 25 via a data read switch 27 to a liquid crystal cell section. Image data is read through a data read buffer 26, and the image data is written to the memory section with no influence of the pixel potential on the held data in the memory circuit 25. This make it possible for the liquid display device to have a large margin for the variation in the characteristics of the transistors constituting the pixel circuit. Therefore, the variation in image quality due to the variation in transistor characteristics is eliminated.

    Abstract translation: 一种液晶显示装置，其消除了将数据写入存储器部分时的像素电位的影响，并且可以对构成像素电路的晶体管的特性的变化和包括该显示装置的便携式终端具有较大的余量。 具有存储器电路25的像素电路具有两个不同的路径：一个用于通过数据写入开关24从信号线16-i向存储器电路25写入图像数据，另一个用于读取由 存储电路25经由数据读取开关27连接到液晶单元部分。 通过数据读取缓冲器26读取图像数据，并且将图像数据写入存储器部分，而不影响存储器电路25中的保持数据上的像素电位。这使得液体显示装置可以具有 构成像素电路的晶体管的特性变化的大余量。 因此，消除了由于晶体管特性的变化引起的图像质量的变化。

    ELECTROOPTIC DEVICE, SUBSTRATE THEREFOR, ELECTRONIC DEVICE, AND PROJECTION DISPLAY
    98.
    发明申请
    ELECTROOPTIC DEVICE, SUBSTRATE THEREFOR, ELECTRONIC DEVICE, AND PROJECTION DISPLAY 审中-公开
    电子设备，其基板，电子设备和投影显示器

    公开(公告)号：WO00008626A1

    公开(公告)日：2000-02-17

    申请号：PCT/JP1999/004195

    申请日：1999-08-03

    IPC: G02F1/1362 ,  G09G3/36 ,  G02F1/133 ,  G09F9/00 ,  G09G3/20

    CPC classification number: G09G3/3659 ,  G02F1/1362 ,  G09G3/3614 ,  G09G2300/0852 ,  G09G2300/0857 ,  G09G2310/0235 ,  G09G2310/061

    Abstract: A substrate for an electrooptic device comprises a signal electrode, a first sample-and-hold circuit connected electrically with the signal electrode, a second sample-and-hold circuit connected electrically with the signal electrode, a pixel driver circuit, and pixel electrodes connected electrically with the pixel driver circuit. When a signal belonging to the (N+1)th image is applied to the signal electrode, the pixel driver circuit applies voltage to the pixel electrode for a first predetermined period based on the signal belonging to Nth image stored in the first sample-and-hold circuit. In the first predetermined period, the second sample-and-hold circuit stores the signal belonging to the (N+1)th image. When a signal belonging to the (N+2)th image is applied to the signal electrode, the pixel driver circuit applies voltage to the pixel electrode for a second predetermined period based on the signal belonging to (N+1)th image stored in the second sample-and-hold circuit. In the second predetermined period, the first sample-and-hold circuit stores the signal belonging to the (N+2)th image.

    Abstract translation: 电光装置的基板包括信号电极，与信号电极电连接的第一采样保持电路，与信号电极电连接的第二采样和保持电路，像素驱动电路和连接的像素电极 与像素驱动电路电连接。 当属于第（N + 1）图像的信号被施加到信号电极时，像素驱动电路基于属于第一样本中存储的第N个图像的信号将电压施加到像素电极第一预定周期， -hold电路。 在第一预定时段中，第二采样保持电路存储属于第（N + 1）个图像的信号。 当属于第（N + 2）图像的信号被施加到信号电极时，像素驱动电路基于属于第（N + 2）图像中存储的第（N + 1）个图像的信号，向像素电极施加电压第二预定周期 第二采样保持电路。 在第二预定时段中，第一采样和保持电路存储属于第（N + 2）个图像的信号。

    INTERNAL ROW SEQUENCER FOR REDUCING BANDWIDTH AND PEAK CURRENT REQUIREMENTS IN A DISPLAY DRIVER CIRCUIT
    99.
    发明申请
    INTERNAL ROW SEQUENCER FOR REDUCING BANDWIDTH AND PEAK CURRENT REQUIREMENTS IN A DISPLAY DRIVER CIRCUIT 审中-公开
    用于降低显示驱动电路中的带宽和峰值电流要求的内部串行数字

    公开(公告)号：WO99049444A1

    公开(公告)日：1999-09-30

    申请号：PCT/US1999/006261

    申请日：1999-03-22

    IPC: G09G3/20 ,  G09G3/36 ,  G09G3/18 ,  G09G1/16

    CPC classification number: G09G3/2085 ,  G09G3/20 ,  G09G3/3659 ,  G09G2300/0842 ,  G09G2300/0857 ,  G09G2310/02 ,  G09G2310/0221 ,  G09G2310/0254 ,  G09G2310/0262 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2330/025 ,  G09G2370/08

    Abstract: A display driver circuit (1100) includes a word line sequencer for providing a series of row addresses, and a row decoder (504) for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer (802) provides a series of path addresses which are used by an optional data router (804) to route data to particular sub-rows of display (1102). Additionally, an optional sub-row sequencer (1106) provides a series of sub-row addresses to an optional sub-row decoder (1108), which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals. In various embodiments, the row sequencer (506), the sub-row sequencer (1106), and/or the data path sequencer (802) is/are responsive to data load instructions from a system, such that no Array Write commands are required to write data to a display (1102).

    Abstract translation: 显示驱动器电路（1100）包括用于提供一系列行地址的字线定序器，以及行解码器（504），用于解码每个行地址，并在多个输出端子的相应的一个输出端上断言写入信号。 可选的数据路径定序器（802）提供一系列路由地址，这些路由地址由可选的数据路由器（804）用来将数据路由到特定的显示子行（1102）。 此外，可选的子行排序器（1106）向可选的子行解码器（1108）提供一系列子行地址，该子行解码器解码子行地址中的每一个，并且在第二个对应的多个 的输出端子。 在各种实施例中，行定序器（506），子行定序器（1106）和/或数据路径定序器（802）响应于来自系统的数据加载指令，使得不需要阵列写入命令 以将数据写入显示器（1102）。

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