公开(公告)号：WO2004088848A2

公开(公告)日：2004-10-14

申请号：PCT/US2004/009349

申请日：2004-03-26

Applicant: ESS TECHNOLOGY INC. ,  MALLINSON, Andrew, Martin

Inventor： MALLINSON, Andrew, Martin

IPC: H03M

CPC classification number: H03M1/0604 ,  H03M1/682 ,  H03M1/765

Abstract: An improved segmented analog to digital converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract translation: 提供了一种改进的分段模数转换器，其配置有补偿次级或连续分段元件中的电流的新颖方法。 在操作中，双电流装置最初加载，随后卸载连接到次级或连续电压分段元件的级联的电阻网络，以防止主要或先前元件的精确操作的扰动。 与常规方法相比，改进的转换器不需要缓冲器或放大器来隔离次级和连续的电压分段元件与初级元件或先前元件。

公开(公告)号：WO2004088642A3

公开(公告)日：2004-10-14

申请号：PCT/US2004/009351

申请日：2004-03-26

Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

Inventor： MALLINSON, Andrew, Martin

IPC: H03C3/00

Abstract: A signal processor (100) has a plurality of channels, each channel configured to receive an input signal stream (S1~S8), to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters (LPF~LPF_4) configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control (Gain J) configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter (214) to invert the in-phase filtered reference signal and means to multiply (216) the quadrature gain adjusted output signal.

公开(公告)号：WO2004088642A2

公开(公告)日：2004-10-14

申请号：PCT/US2004009351

申请日：2004-03-26

Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN

Inventor： MALLINSON ANDREW MARTIN

IPC: G11B20060101 ,  H03C3/00 ,  H03H7/30 ,  H03H17/02 ,  H04B1/02 ,  H04L27/06 ,  H04L27/20 ,  H04L27/26 ,  G11B

CPC classification number: H03H17/027 ,  H03H2218/06 ,  H04L27/2601

Abstract: A signal processor has a plurality of channels, each channel configured to receive an input signal stream, to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter to invert the in-phase filtered reference signal and means to multiply the quadrature gain adjusted output signal.

Abstract translation: 信号处理器具有多个通道，每个通道被配置为接收输入信号流，以将信号减小到直流信号，并根据流信号处理该信号。 每个通道还具有多个低通滤波器，其被配置为用第一低通滤波器对同相和正交相位调制器输出进行滤波，并对基准正交信号进行滤波;以及增益控制，被配置为用增益调节的输出信号重新调制， 滤波后的正交信号。 处理器还包括反相器，用于反相同相滤波的参考信号，以及将正交增益调整的输出信号相乘的装置。

公开(公告)号：WO2004068719A1

公开(公告)日：2004-08-12

申请号：PCT/US2003/009041

申请日：2003-03-26

Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

Inventor： MALLINSON, Andrew, Martin

IPC: H03M1/36

CPC classification number: H03M1/0854 ,  H03M1/1235 ,  H03M1/144 ,  H03M1/206 ,  H03M1/367

Abstract: An analog-to-digital converter (300) in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom.

Abstract translation: 一种模数转换器（300），其中多个比较器中的每一个以逐次逼近的方式被选择性地使能或禁止，并且来自那些比较器的输出相加在一起从而产生数字信号。

公开(公告)号：WO2004013896A2

公开(公告)日：2004-02-12

申请号：PCT/US0324220

申请日：2003-08-01

Applicant: ESS TECHNOLOGY INC

Inventor： CHAN MING HONG ,  HUANG ELIM ,  HO ANDY

IPC: G06F13/362 ,  G06F13/00 ,  G06F13/42 ,  H01L

CPC classification number: G06F13/4213

Abstract: A method for controlling communication on a bus connecting a first processor, a second processor, and a device. The method transmits a first control signal from the first processor to the second processor via a control signal line, causing a bus connection of the second processor to enter a high-impedance state, transfers data between the device and the first processor via the bus, then setting a bus connection of the first processor to the high-impedance state, and transmits a second control signal from the first processor to the second processor via the control signal line, causing the bus connection of the second processor to exit the high-impedance state.

Abstract translation: 一种用于控制连接第一处理器，第二处理器和设备的总线上的通信的方法。 该方法经由控制信号线将第一控制信号从第一处理器发送到第二处理器，使得第二处理器的总线连接进入高阻态，经由总线在设备和第一处理器之间传送数据， 然后将第一处理器的总线连接设置为高阻抗状态，并且经由控制信号线将第二控制信号从第一处理器发送到第二处理器，使得第二处理器的总线连接退出高阻抗 州。

公开(公告)号：WO2003088498A1

公开(公告)日：2003-10-23

申请号：PCT/US2003/005813

申请日：2003-02-25

Applicant: ESS TECHNOLOGY, INC.

Inventor： MALLINSON, Andrew, Martin

IPC: H03M1/36

CPC classification number: H03M1/367

Abstract: A differential input flash analog to digital converter (500) in which an array of comparators "C1,1-C1,5" is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signals "Vin(a)-Vin(b)" across an impedance network "R1-R5". The comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range.

Abstract translation: 差分输入闪存模数转换器（500），其中比较器“C1,1-C1,5”的阵列被连接以比较通过应用差分输入信号“Vin”生成的这种信号的抛物面分布内的参考信号 （a）-Vin（b）“跨阻抗网络”R1-R5“。 所述比较器阵列包括至少两个比较器，所述第一多个比较器比较由第一步长分隔的参考节点对，所述第二多个比较器比较由第二步长分隔的参考节点对。 优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时才使可用比较范围最大化。

公开(公告)号：WO2015100345A2

公开(公告)日：2015-07-02

申请号：PCT/US2014/072197

申请日：2014-12-23

Applicant: ESS TECHNOLOGY, INC.

Inventor： MALLINSON, A., Martin

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/618

Abstract: A voltage regulator for providing a constant voltage to a circuit is described in which a series regulator acts as the current source for a shunt regulator and the series regulator in turn is controlled by the current diverted from the output by the shunt regulator. The current being diverted by the shunt regulator is measured, either directly or by measuring a related operating parameter. When current below or above a certain desired amount is being diverted from the load by the shunt regulator, a signal is sent to the series regulator causing the series regulator to provide more or less current respectively, so that the shunt regulator again diverts the desired amount of current and the output voltage remains constant. This configuration results in efficiency near that of a series regulator while maintaining the better frequency response of a shunt regulator.

Abstract translation: 描述了一种用于向电路提供恒定电压的电压调节器，其中串联调节器用作分流调节器的电流源，而串联调节器又由来自输出端的电流控制 通过分流调节器。 直接或通过测量相关操作参数来测量由分流调节器转移的电流。 当低于或高于特定期望值的电流被分流调节器从负载转移时，信号被发送到串联调节器，使得串联调节器分别提供更多或更少的电流，使得分流调节器再次转移期望的量 的电流和输出电压保持不变。 这种配置的效率接近串联稳压器的效率，同时保持并联稳压器的更好的频率响应。

公开(公告)号：WO2011069229A1

公开(公告)日：2011-06-16

申请号：PCT/CA2009/001817

申请日：2009-12-11

Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Martin ,  FORMAN, Dustin

Inventor： MALLINSON, Martin ,  FORMAN, Dustin

IPC: H03D7/00 ,  H03H17/02 ,  H04B1/10

CPC classification number: H04B1/302 ,  H03H15/00

Abstract: A virtual Weaver architecture filter is implemented using a sampling mixer that successively processes samples of the input signal in round-robin fashion and provides a sum of the samples as multiplied by coefficients emulating quadrature sinusoidal waveforms. A virtual rather than actual local oscillator is reliably implemented without mismatch. Filtering between the Weaver mixers is eliminated in favour of filtering at the sampling input and effective time division multiplexing is achieved by selecting between resistor combinations that implement different scaling coefficients, resulting in an efficient analog implementation of a virtual Weaver architecture.

Abstract translation: 虚拟韦弗架构滤波器使用采样混频器来实现，该采样混频器以循环方式连续地处理输入信号的样本，并将样本的和乘以仿真正交正弦波形的系数。 虚拟而不是实际的本地振荡器可靠地实现而不匹配。 消除了韦弗混频器之间的滤波，有利于在采样输入处的滤波，并且通过在实现不同缩放系数的电阻器组合之间进行选择来实现有效的时分复用，从而实现虚拟韦弗架构的有效模拟实现。

公开(公告)号：WO2010088293A3

公开(公告)日：2010-08-05

申请号：PCT/US2010/022266

申请日：2010-01-27

Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

Inventor： MALLINSON, Andrew, Martin

IPC: H03H17/00

Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non- radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital- to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.

公开(公告)号：WO2007133345A3

公开(公告)日：2008-03-27

申请号：PCT/US2007008062

申请日：2007-04-03

Applicant: ESS TECHNOLOGY INC ,  MANN RICHARD A

Inventor： MANN RICHARD A

IPC: H01L27/00 ,  H04N5/353 ,  H04N5/355 ,  H04N5/374 ,  H04N5/378

CPC classification number: H04N5/37457 ,  H01L27/14643

Abstract: An exemplary image sensor (100) comprises a photodetector (122,124,126,128) proximate to a pixel site (102), and a light meter (104) proximate to the pixel site configured to approximate an initial charge acquired by the photodetector at the end of a first integration period of a frame exposure period. A reset circuit (106) resets the photodetector if the approximated initial charge acquired by the photodetector exceeds a threshold. A readout circuit (108) detects a final charge acquired by the photodetector at the end of a second integration period of the frame exposure period. If the photodetector was reset, the readout circuit adjusts the final exposure to account for exposure prior to the photodetector having been reset.

Abstract translation: 示例性图像传感器（100）包括靠近像素位置（102）的光电检测器（122,124,126,128）和靠近像素位置的光计（104），被配置为近似由第一 帧曝光期的积分期。 如果由光电检测器获取的近似初始电荷超过阈值，则复位电路（106）复位光电检测器。 读出电路（108）在帧曝光期间的第二积分期间结束时检测由光检测器获取的最终电荷。 如果光电检测器被复位，则在光电检测器被复位之前，读出电路调节最终曝光以考虑曝光。