公开(公告)号：WO2008124094A1

公开(公告)日：2008-10-16

申请号：PCT/US2008/004446

申请日：2008-04-04

Applicant: ATMEL CORPORATION ,  SURICO, Stefano ,  SIVERO, Stefano ,  BARTOLI, Simone ,  PASSERINI, Marco

Inventor： SURICO, Stefano ,  SIVERO, Stefano ,  BARTOLI, Simone ,  PASSERINI, Marco

IPC: G06F11/00

CPC classification number: G11C16/10

Abstract: Some embodiments disclosed comprise apparatus and methods relating to a nonvolatile memory comprising an input output buffer; a latch circuit coupled to the input/output buffers; a memory array having nonvolatile memory cells coupled to an input/output buffer; a command user interface coupled to the input/output buffer and the latch circuit; a microcontroller coupled to the command user interface; a read-only memory storing instructions to be executed by the microcontroller; and a switch-instruction circuitry coupled to the latch circuit, the read-only memory and the digital control circuitry to selectively provide instructions to the microcontroller from the read-only memory and to selectively provide substitute instructions under control of the command user interface, the substitute instructions received at the input/output buffer from an external source. Other embodiments and methods are disclosed.

Abstract translation: 公开的一些实施例包括涉及包括输入输出缓冲器的非易失性存储器的装置和方法; 耦合到输入/输出缓冲器的锁存电路; 具有耦合到输入/输出缓冲器的非易失性存储单元的存储器阵列; 耦合到输入/输出缓冲器和锁存电路的命令用户界面; 耦合到命令用户界面的微控制器; 存储由微控制器执行的指令的只读存储器; 以及耦合到所述锁存电路，所述只读存储器和所述数字控制电路的开关指令电路，用于从所述只读存储器选择性地向所述微控制器提供指令，并且在所述命令用户界面的控制下选择性地提供替代指令， 从外部源代替在输入/输出缓冲器处接收的指令。 公开了其他实施例和方法。

公开(公告)号：WO2008055184A3

公开(公告)日：2008-06-19

申请号：PCT/US2007083063

申请日：2007-10-30

Applicant: ATMEL CORP ,  SIVERO STEFANO ,  MARSELLA MIRELLA ,  CHINOSI MAURO ,  BOSISIO GIORGIO

Inventor： SIVERO STEFANO ,  MARSELLA MIRELLA ,  CHINOSI MAURO ,  BOSISIO GIORGIO

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.

Abstract translation: 信号发生器电路被配置为产生用于存储器阵列的程序信号。 程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。 瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

公开(公告)号：WO2008055183A2

公开(公告)日：2008-05-08

申请号：PCT/US2007083062

申请日：2007-10-30

Applicant: ATMEL CORP ,  SIVERO STEFANO ,  SURICO STEFANO ,  CASER FABIO TASSAN ,  CHINOSI MAURO

Inventor： SIVERO STEFANO ,  SURICO STEFANO ,  CASER FABIO TASSAN ,  CHINOSI MAURO

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.

Abstract translation: 存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致 晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

公开(公告)号：WO2006023730A3

公开(公告)日：2006-05-11

申请号：PCT/US2005029567

申请日：2005-08-16

Applicant: ATMEL CORP ,  ODDONE GIORGIO ,  SIVERO STEFANO ,  BOSISIO GIORGIO ,  BETTINI ANDREA

Inventor： ODDONE GIORGIO ,  SIVERO STEFANO ,  BOSISIO GIORGIO ,  BETTINI ANDREA

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: A fast power-on band-gap reference circuit includes a band-gap logic and a band-gap dummy logic. During power-on, both the band-gap logic and the band-gap dummy logic are activated and charges the capacitance of a band-gap line. When an output of the band-gap logic reaches a predetermined value, the band-gap dummy logic is deactivated. Thus, the band-gap dummy logic, with a high drive capability, charges the band-gap capacitance at the same time the band-gap logic starts to generate the compensate temperature voltage. In this manner, the band-gap reference circuit reaches its stable, functional state faster than conventional circuits, in the range of a few microseconds.

Abstract translation: 快速上电带隙参考电路包括带隙逻辑和带隙虚拟逻辑。 在上电期间，带隙逻辑和带隙虚拟逻辑都被激活并对带隙线的电容进行充电。 当带隙逻辑的输出达到预定值时，带隙虚拟逻辑被去激活。 因此，具有高驱动能力的带隙虚拟逻辑在带隙逻辑开始产生补偿温度电压的同时对带隙电容进行充电。 以这种方式，带隙参考电路在几微秒的范围内达到其比常规电路更稳定的功能状态。

公开(公告)号：WO2006044942A3

公开(公告)日：2006-04-27

申请号：PCT/US2005/037546

申请日：2005-10-18

Applicant: ATMEL CORPORATION ,  FRULIO, Massimiliano ,  SIVERO, Stefano ,  CASER, Fabio, Tassan ,  CHINOSI, Mauro

Inventor： FRULIO, Massimiliano ,  SIVERO, Stefano ,  CASER, Fabio, Tassan ,  CHINOSI, Mauro

IPC: G11C8/00

Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

公开(公告)号：WO2006041790A2

公开(公告)日：2006-04-20

申请号：PCT/US2005/035528

申请日：2005-09-30

Applicant: ATMEL CORPORATION ,  SIVERO, Stefano ,  BARTOLI, Simone ,  TASSAN CASER, Fabio ,  RIVA, REGGIORI, Riccardo

Inventor： SIVERO, Stefano ,  BARTOLI, Simone ,  TASSAN CASER, Fabio ,  RIVA, REGGIORI, Riccardo

CPC classification number: G11C7/1051 ,  G11C7/1012 ,  G11C7/1021 ,  G11C16/24

Abstract: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.

Abstract translation: 用于闪存器件的列解码的改进方法和设备利用长度大于逻辑页长度的突发页。 当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。 只有当读取跨越突发页面边界时，存储器件才进入等待状态。 这使存储器件进入等待状态的时间量最小化。 在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。 不需要对架构或列解码器选择器的数量进行更改。 因此，同步读取期间的存储器访问时间得到改善。