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    ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE
    1.
    发明申请
    ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE 审中-公开
    存储器装置的电荷泵电路中的空闲状态的自适应调节器

    公开(公告)号：WO2008045411A3

    公开(公告)日：2008-11-20

    申请号：PCT/US2007021534

    申请日：2007-10-09

    Applicant: ATMEL CORP ,  PASSERINI MARCO ,  SIVERO STEFANO ,  SACCO ANDREA ,  MARZIANI MONICA

    Inventor： PASSERINI MARCO ,  SIVERO STEFANO ,  SACCO ANDREA ,  MARZIANI MONICA

    IPC: G11C5/14

    CPC classification number: G11C7/02 ,  G11C5/145

    Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.

    Abstract translation: 公开了一种用于改进电子设备的性能的装置和方法。 当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。 空闲状态减少了由线路或节点中的突然电压变化引起的开关干扰的不良影响。

    PROGRAMMING PULSE GENERATOR
    2.
    发明申请
    PROGRAMMING PULSE GENERATOR 审中-公开
    编程脉冲发生器

    公开(公告)号：WO2008055184A2

    公开(公告)日：2008-05-08

    申请号：PCT/US2007/083063

    申请日：2007-10-30

    Applicant: ATMEL CORPORATION ,  SIVERO, Stefano ,  MARSELLA, Mirella ,  CHINOSI, Mauro ,  BOSISIO, Giorgio

    Inventor： SIVERO, Stefano ,  MARSELLA, Mirella ,  CHINOSI, Mauro ,  BOSISIO, Giorgio

    IPC: G11C16/12

    CPC classification number: G11C16/12

    Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.

    Abstract translation: 信号发生器电路被配置为产生用于存储器阵列的程序信号。 程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。 瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

    CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS
    3.
    发明申请
    CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 审中-公开
    用于产生多个输出电压的充电泵

    公开(公告)号：WO2008073862A2

    公开(公告)日：2008-06-19

    申请号：PCT/US2007/086912

    申请日：2007-12-10

    Applicant: ATMEL CORPORATION ,  FRULIO, Massimiliano ,  SIVERO, Stefano ,  PASSERINI, Marco ,  TASSAN, Caser, Fabio

    Inventor： FRULIO, Massimiliano ,  SIVERO, Stefano ,  PASSERINI, Marco ,  TASSAN, Caser, Fabio

    IPC: G05F1/10

    CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C16/30 ,  H02M2001/007 ,  H02M2001/009

    Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.

    Abstract translation: 用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。 第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。 提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。 第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

    METHOD AND APPARATUS FOR FAST POWER-ON BAND-GAP REFERENCE
    7.
    发明申请
    METHOD AND APPARATUS FOR FAST POWER-ON BAND-GAP REFERENCE 审中-公开
    用于快速通电带隙参考的方法和设备

    公开(公告)号：WO2006023730A2

    公开(公告)日：2006-03-02

    申请号：PCT/US2005/029567

    申请日：2005-08-16

    Applicant: ATMEL CORPORATION ,  ODDONE, Giorgio ,  SIVERO, Stefano ,  BOSISIO, Giorgio ,  BETTINI, Andrea

    Inventor： ODDONE, Giorgio ,  SIVERO, Stefano ,  BOSISIO, Giorgio ,  BETTINI, Andrea

    IPC: G05F1/10

    CPC classification number: G05F3/30

    Abstract: A fast power-on band-gap reference circuit includes a band-gap logic and a band-gap dummy logic. During power-on, both the band-gap logic and the band-gap dummy logic are activated and charges the capacitance of a band-gap line. When an output of the band-gap logic reaches a predetermined value, the band-gap dummy logic is deactivated. Thus, the band-gap dummy logic, with a high drive capability, charges the band-gap capacitance at the same time the band-gap logic starts to generate the compensate temperature voltage. In this manner, the band-gap reference circuit reaches its stable, functional state faster than conventional circuits, in the range of a few microseconds.

    Abstract translation: 快速通电带隙参考电路包括带隙逻辑和带隙虚拟逻辑。 在上电期间，带隙逻辑和带隙虚拟逻辑都被激活并为带隙线的电容充电。 当带隙逻辑的输出达到预定值时，带隙虚拟逻辑被去激活。 因此，具有高驱动能力的带隙虚拟逻辑在带隙逻辑开始产生补偿温度电压的同时对带隙电容充电。 以这种方式，带隙参考电路在几微秒范围内比传统电路更快地达到其稳定的功能状态。

    CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS
    8.
    发明申请
    CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 审中-公开
    用于产生多个输出电压电平的电荷泵

    公开(公告)号：WO2008073862A3

    公开(公告)日：2008-12-18

    申请号：PCT/US2007086912

    申请日：2007-12-10

    Applicant: ATMEL CORP ,  FRULIO MASSIMILIANO ,  SIVERO STEFANO ,  PASSERINI MARCO ,  TASSAN CASER FABIO

    Inventor： FRULIO MASSIMILIANO ,  SIVERO STEFANO ,  PASSERINI MARCO ,  TASSAN CASER FABIO

    IPC: H03L7/06 ,  G05F1/10 ,  G05F3/02 ,  H02M3/18 ,  H02M7/00

    CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C16/30 ,  H02M2001/007 ,  H02M2001/009

    Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.

    Abstract translation: 用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联的电荷泵级，第一组中的第一电荷泵级的输入由电源电压驱动。 第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。 提供第二组级联的电荷泵级，第二组的第一电荷泵级的输入从第一组的最后电荷泵级的输出驱动。 第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

    COLUMN DECODING ARCHITECTURE FOR FLASH MEMORIES
    10.
    发明申请
    COLUMN DECODING ARCHITECTURE FOR FLASH MEMORIES 审中-公开
    闪存记忆体解码架构

    公开(公告)号：WO2006041790A3

    公开(公告)日：2007-11-15

    申请号：PCT/US2005035528

    申请日：2005-09-30

    Applicant: ATMEL CORP ,  SIVERO STEFANO ,  BARTOLI SIMONE ,  TASSAN CASER FABIO ,  RIVA REGGIORI RICCARDO

    Inventor： SIVERO STEFANO ,  BARTOLI SIMONE ,  TASSAN CASER FABIO ,  RIVA REGGIORI RICCARDO

    IPC: G11C8/00

    CPC classification number: G11C7/1051 ,  G11C7/1012 ,  G11C7/1021 ,  G11C16/24

    Abstract: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.

    Abstract translation: 用于闪存器件的列解码的改进方法和设备利用长度大于逻辑页长度的突发页。 当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。 只有当读取跨越突发页面边界时，存储器件才进入等待状态。 这使存储器件进入等待状态的时间量最小化。 在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。 不需要对架构或列解码器选择器的数量进行更改。 因此，同步读取期间的存储器访问时间得到改善。

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