公开(公告)号：WO2008055183A3

公开(公告)日：2008-05-08

申请号：PCT/US2007/083062

申请日：2007-10-30

Applicant: ATMEL CORPORATION ,  SIVERO, Stefano ,  SURICO, Stefano ,  CASER, Fabio Tassan ,  CHINOSI, Mauro

Inventor： SIVERO, Stefano ,  SURICO, Stefano ,  CASER, Fabio Tassan ,  CHINOSI, Mauro

IPC: G11C16/10

Abstract: A memory device generates a select voltage (V[0]) and an unselect voltage (V[1]) on bit lines and generates a bit line select voltage (V[1]-E) having a magnitude less than the unselect voltage (V[1]) so that the application of the bit line select voltage to a gate of a transistor (110) receiving the select voltage (V[0] ) causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage (V[1]) biases the transistor off.

公开(公告)号：WO2006044942A2

公开(公告)日：2006-04-27

申请号：PCT/US2005037546

申请日：2005-10-18

Applicant: ATMEL CORP ,  FRULIO MASSIMILIANO ,  SIVERO STEFANO ,  CASER FABIO TASSAN ,  CHINOSI MAURO

Inventor： FRULIO MASSIMILIANO ,  SIVERO STEFANO ,  CASER FABIO TASSAN ,  CHINOSI MAURO

IPC: G11C8/00

CPC classification number: G11C7/18 ,  G11C7/06 ,  G11C2207/002 ,  G11C2207/005

Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

Abstract translation: 描述了一种用于提供多存储体存储器的方法和系统。 该方法和系统包括提供多个银行。 多个组中的每一个包括至少一个包括多个存储单元和模拟感测电路的阵列。 该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

公开(公告)号：WO2008055184A2

公开(公告)日：2008-05-08

申请号：PCT/US2007/083063

申请日：2007-10-30

Applicant: ATMEL CORPORATION ,  SIVERO, Stefano ,  MARSELLA, Mirella ,  CHINOSI, Mauro ,  BOSISIO, Giorgio

Inventor： SIVERO, Stefano ,  MARSELLA, Mirella ,  CHINOSI, Mauro ,  BOSISIO, Giorgio

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.

Abstract translation: 信号发生器电路被配置为产生用于存储器阵列的程序信号。 程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。 瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

公开(公告)号：WO2006119327A2

公开(公告)日：2006-11-09

申请号：PCT/US2006/016902

申请日：2006-05-03

Applicant: ATMEL CORPORATION ,  SURICO, Stefano ,  MARSELLA, Mirella ,  MARZIANI, Monica ,  CHINOSI, Mauro

Inventor： SURICO, Stefano ,  MARSELLA, Mirella ,  MARZIANI, Monica ,  CHINOSI, Mauro

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C16/3468

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract translation: 在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置电压序列发生器，用于在用于非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。 以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。 更具体地，引入完全兼容的电压序列生成，其可以应用于被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换进行有效且省时的管理。

公开(公告)号：WO2008055184A3

公开(公告)日：2008-06-19

申请号：PCT/US2007083063

申请日：2007-10-30

Applicant: ATMEL CORP ,  SIVERO STEFANO ,  MARSELLA MIRELLA ,  CHINOSI MAURO ,  BOSISIO GIORGIO

Inventor： SIVERO STEFANO ,  MARSELLA MIRELLA ,  CHINOSI MAURO ,  BOSISIO GIORGIO

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.

Abstract translation: 信号发生器电路被配置为产生用于存储器阵列的程序信号。 程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。 瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

公开(公告)号：WO2008055183A2

公开(公告)日：2008-05-08

申请号：PCT/US2007083062

申请日：2007-10-30

Applicant: ATMEL CORP ,  SIVERO STEFANO ,  SURICO STEFANO ,  CASER FABIO TASSAN ,  CHINOSI MAURO

Inventor： SIVERO STEFANO ,  SURICO STEFANO ,  CASER FABIO TASSAN ,  CHINOSI MAURO

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.

Abstract translation: 存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致 晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

公开(公告)号：WO2006044942A3

公开(公告)日：2006-04-27

申请号：PCT/US2005/037546

申请日：2005-10-18

Applicant: ATMEL CORPORATION ,  FRULIO, Massimiliano ,  SIVERO, Stefano ,  CASER, Fabio, Tassan ,  CHINOSI, Mauro

Inventor： FRULIO, Massimiliano ,  SIVERO, Stefano ,  CASER, Fabio, Tassan ,  CHINOSI, Mauro

IPC: G11C8/00

Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

公开(公告)号：WO2008089158A3

公开(公告)日：2009-12-30

申请号：PCT/US2008051024

申请日：2008-01-14

Applicant: ATMEL CORP ,  BEDARIDA LORENZO ,  PELLI GABRIELE ,  BARTOLI SIMONE ,  CHINOSI MAURO

Inventor： BEDARIDA LORENZO ,  PELLI GABRIELE ,  BARTOLI SIMONE ,  CHINOSI MAURO

IPC: G11C7/08

CPC classification number: G11C7/062 ,  G11C7/02 ,  G11C7/067 ,  G11C16/26 ,  G11C2207/063

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract translation: 具有电流偏移功能的感测电路。 在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。 感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。 感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。 根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

公开(公告)号：WO2008089158A2

公开(公告)日：2008-07-24

申请号：PCT/US2008/051024

申请日：2008-01-14

Applicant: ATMEL CORPORATION ,  BEDARIDA, Lorenzo ,  PELLI, Gabriele ,  BARTOLI, Simone ,  CHINOSI, Mauro

Inventor： BEDARIDA, Lorenzo ,  PELLI, Gabriele ,  BARTOLI, Simone ,  CHINOSI, Mauro

IPC: G11C7/08

CPC classification number: G11C7/062 ,  G11C7/02 ,  G11C7/067 ,  G11C16/26 ,  G11C2207/063

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract translation: 具有电流偏移功能的感测电路。 在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。 感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。 感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。 根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

公开(公告)号：WO2006119327A3

公开(公告)日：2007-12-13

申请号：PCT/US2006016902

申请日：2006-05-03

Applicant: ATMEL CORP ,  SURICO STEFANO ,  MARSELLA MIRELLA ,  MARZIANI MONICA ,  CHINOSI MAURO

Inventor： SURICO STEFANO ,  MARSELLA MIRELLA ,  MARZIANI MONICA ,  CHINOSI MAURO

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C16/3468

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract translation: 在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。 以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。 更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。