公开(公告)号：WO2011044515A3

公开(公告)日：2011-04-14

申请号：PCT/US2010/052074

申请日：2010-10-08

Applicant: VIOLIN MEMORY, INC. ,  BENNETT, Jon, C.R.

Inventor： BENNETT, Jon, C.R.

IPC: G06F12/16 ,  G06F13/14

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

公开(公告)号：WO2009032751A3

公开(公告)日：2009-05-07

申请号：PCT/US2008074628

申请日：2008-08-28

Applicant: VIOLIN MEMORY INC ,  ADELMAN MAXIM ,  BENNETT JON C R

Inventor： ADELMAN MAXIM ,  BENNETT JON C R

IPC: G06F12/00

CPC classification number: G11C11/4076 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0688 ,  G06F3/0689 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4074 ,  G11C2211/4067 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.

Abstract translation: 描述了一种存储器系统，其中多个存储器模块连接到存储器控制器。 根据内存模块执行的功能，每个内存模块的电源状态都受到控制。 当没有对特定存储器模块执行读取或写入操作时，电路的至少一部分可以以较低功率模式操作。 与存储器模块相关联的存储器电路可以通过禁用时钟而置于低功率模式。 当存储器电路处于较低功率模式时，通过发出刷新命令，通过启用时钟，发出刷新命令，并且在完成刷新操作之后禁用时钟，可以保证存储器电路数据完整性。

公开(公告)号：WO2014163620A1

公开(公告)日：2014-10-09

申请号：PCT/US2013/034938

申请日：2013-04-02

Applicant: VIOLIN MEMORY, INC.

Inventor： DE LA IGLESIA, Erik

IPC: G11C7/00 ,  G06F13/14

CPC classification number: G06F13/1642 ,  G06F3/06 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/1626 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: A storage access system provides consistent memory access times for storage media with inconsistent access latency and reduces bottlenecks caused by the variable time delays during memory write operations. Data is written iteratively into multiple different media devices to prevent write operations from blocking all other memory access operations. The multiple copies of the same data then allow subsequent read operations to avoid the media devices currently servicing the write operations. Write operations can be aggregated together to improve the overall write performance to a storage media. A performance index determines how many media devices store the same data. The number of possible concurrent reads varies according to the number of media devices storing the data. Therefore, the performance index provides different selectable Quality of Service (QoS) for data in the storage media.

Abstract translation: 存储访问系统为访问延迟不一致的存储介质提供一致的内存访问时间，并减少在内存写入操作期间由可变时间延迟引起的瓶颈。 将数据迭代地写入多个不同的媒体设备，以防止写入操作阻止所有其他存储器访问操作。 相同数据的多个副本然后允许后续读取操作以避免当前正在为写入操作服务的媒体设备。 可以将写入操作聚合在一起，以提高对存储介质的整体写入性能。 性能指标确定多少媒体设备存储相同的数据。 可能的并发读取的数量根据存储数据的媒体设备的数量而变化。 因此，性能指标为存储介质中的数据提供不同的可选服务质量（QoS）。

公开(公告)号：WO2014142804A1

公开(公告)日：2014-09-18

申请号：PCT/US2013/030410

申请日：2013-03-12

Applicant: VIOLIN MEMORY, INC.

Inventor： DE LA IGLESIA, Erik

IPC: G06F12/02

CPC classification number: G06F3/0689 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0658

Abstract: A storage proxy monitors storage access operations. Different address alignments are identified between the storage access operations and data blocks in a storage media. A dominant one of the address alignments is identified. Data blocks are mapped into the storage media to remove the dominant address alignment. An array of counters can be used to track the address alignments for different storage access sizes and the address alignment associated with the highest number of storage access operations is used as the dominant address alignment.

Abstract translation: 存储代理监视存储访问操作。 在存储介质中的存储访问操作和数据块之间识别不同的地址对齐。 确定地址对齐中的主导地位。 将数据块映射到存储介质中以消除主要地址对齐。 可以使用一组计数器来跟踪不同存储访问大小的地址对齐，并且将与最高数量的存储访问操作相关联的地址对齐用作主要地址对齐。

公开(公告)号：WO2014039424A1

公开(公告)日：2014-03-13

申请号：PCT/US2013/057794

申请日：2013-09-03

Applicant: VIOLIN MEMORY, INC.

Inventor： SISLER, John, R. ,  OTTESEN, John, C. ,  BACA, Russell, T. ,  FRICKER, Jean-phillipe

IPC: G06F1/26

CPC classification number: H02J9/061 ,  H02J1/108 ,  H05K7/14 ,  H05K7/1492 ,  Y10T307/625

Abstract: Maintenance of reliable and highly available electronic systems to perform servicing and preventive maintenance may need to be performed without interruption of operations. Removal of circuit cards from a chassis may render the connectors on a chassis vulnerable to inadvertent short circuiting of power sources by stray metallic objects. A configuration where the power is removed from a connector as the circuit card is being extracted eliminates his possibility. The control circuits for the power supply connections and the power supplies are themselves redundant so that they may be similarly serviced.

Abstract translation: 可能需要维护可靠且高可用性的电子系统进行维修和预防性维护，而不会中断操作。 从机箱中取出电路卡可能会使机箱上的连接器容易受到杂散金属物体无意中短路电源的影响。 随着电路卡被拔出，电源被从连接器移除的配置消除了他的可能性。 用于电源连接和电源的控制电路本身是多余的，因此可以类似地进行维修。

公开(公告)号：WO2013148915A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/034218

申请日：2013-03-28

Applicant: VIOLIN MEMORY, INC.

Inventor： BENNETT, Jon, C.R. ,  BIEDERMAN, Daniel, C.

IPC: G06F12/02 ,  G06F13/14

CPC classification number: G06F3/0689 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0652 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/121 ,  G06F2212/7208

Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.

Abstract translation: 一种具有多个模块的存储器系统，其操作使得一组存储器模块可以在具有擦除隐藏属性的RAID配置中操作。 RAID组映射到RAID组的每个内存模块中的内存区域。 可以将多于一个的RAID组映射到存储器模块，并且RAID组的擦除操作协调使得擦除操作不重叠。 这可以提高存储器模块与控制器通信的总线的利用率。 在具有增加的存储容量的存储器模块替换存储器模块的情况下，附加存储容量可以被映射到扩展的逻辑地址空间。

公开(公告)号：WO2011081957A3

公开(公告)日：2011-10-20

申请号：PCT/US2010060408

申请日：2010-12-15

Applicant: VIOLIN MEMORY INC ,  TALAGALA NISHA ,  KERCHEVAL BERRY ,  PATTERSON MARTIN ,  PERNICKA EDWARD ,  BOWEN JAMES

Inventor： TALAGALA NISHA ,  KERCHEVAL BERRY ,  PATTERSON MARTIN ,  PERNICKA EDWARD ,  BOWEN JAMES

IPC: G06F12/08 ,  G06F9/06

CPC classification number: G06F12/0246 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/225 ,  G06F2212/7211

Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Abstract translation: 描述了多层缓存管理器和用于管理多层缓存的方法。 多层缓存管理器使高速缓存的数据最初存储在RAM元素中，并选择存储在RAM元素中的缓存数据的一部分以移动到闪存元素。 每个闪存元件被组织为具有块大小的多个写入块，并且其中允许每个写入块的预定义的最大写入数量。 可以基于从闪存设备允许的最大写入数量和高速缓存系统的指定寿命计算的最大写入速率来选择缓存数据的部分。

公开(公告)号：WO2009046300A3

公开(公告)日：2009-05-22

申请号：PCT/US2008078752

申请日：2008-10-03

Applicant: VIOLIN MEMORY INC ,  JONES JAMES H ,  DRUCKER KEVIN D ,  BENNETT JON C R

Inventor： JONES JAMES H ,  DRUCKER KEVIN D ,  BENNETT JON C R

IPC: G06F13/16

CPC classification number: G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract translation: 描述了一种存储器系统，其中存储器模块之间的数据传输时间被管理，使得存储器系统中的指定点之间的总体时间延迟保持恒定。 可以单独管理多车道总线的每条通道，并且在目的地模块处评估数据帧，而不需要在中间模块处进行纠偏。 通过在总线串行数据速率的一个或多个约数处操作通过模块的数据路径，并选择数据路径的采样点来减少通过可能具有切换数据路由的模块的数据传播的时间延迟 接收到的数据，以适应由于温度变化或老化引起的时间延迟的变化。

公开(公告)号：WO2014047382A1

公开(公告)日：2014-03-27

申请号：PCT/US2013/060816

申请日：2013-09-20

Applicant: VIOLIN MEMORY INC.

Inventor： PIGNATELLI, David, J.

IPC: G06F11/22

CPC classification number: G06F12/0246 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/7208

Abstract: A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently. A unique sequence identifier is assigned to a write command and the associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.

Abstract translation: 闪速存储器管理方法和装置提供命令和数据路径的分离，使得可以更有效地使用通信路径。 分配给写入命令的唯一序列标识符，并且在执行命令之前通过比较数据和命令的唯一序列号，在写入存储器之前验证数据和命令的关联数据和关联。 在数据和命令遍历通信路径之后执行该比较。

公开(公告)号：WO2013155368A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/036295

申请日：2013-04-12

Applicant: VIOLIN MEMORY, INC.

Inventor： BENNETT, Jon, C.R.

IPC: G06F12/00 ,  G11C16/02

CPC classification number: G06F12/0292 ,  G06F12/0246 ,  G06F12/0253 ,  G06F17/30218 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses that are declared to be deleted by a user file management system. A series of data structures accounts for the levels of indirection used to manage the correspondence between a user logical block address and the physical location of the data in the memory system and to respond to user read and write requests by efficiently determining the current status of the user logical block address in the frame of reference of the memory system and substantially decoupling the TRIM management from the garbage collection and wear leveling operations.

Abstract translation: 用于管理闪速存储器系统的方法和系统便于使用TRIM或类似操作，以便释放被用户文件管理系统声明为要删除的逻辑块地址的物理存储器空间。 一系列数据结构考虑了用于管理用户逻辑块地址和存储器系统中的数据的物理位置之间的对应关系的间接级别，并通过有效地确定用户的读取和写入请求的当前状态 在存储器系统的参考系中的用户逻辑块地址，并且将TRIM管理与垃圾收集和损耗均衡操作基本上分离。