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    METHOD AND APPARATUS FOR OVER CLOCKING IN A DIGITAL PROCESSING SYSTEM
    21.
    发明申请
    METHOD AND APPARATUS FOR OVER CLOCKING IN A DIGITAL PROCESSING SYSTEM 审中-公开
    在数字处理系统中超时钟的方法和装置

    公开(公告)号：WO2005073828A2

    公开(公告)日：2005-08-11

    申请号：PCT/IB2005050234

    申请日：2005-01-20

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

    Inventor： PESSOLANO FRANCESCO

    IPC: G06F1/00 ,  G06F1/08

    CPC classification number: G06F1/08

    Abstract: A method of determining a maximum optimum clock frequency at which a digital processing system can operate, the method comprising the steps of: generating a clock signal at an initial frequency; increasing said frequency in a step-wise manner and determining the operation of said system each of a selected number of frequencies, until a clock frequency is identified at which said processor does not operate correctly; and identifying a maximum clock frequency at which said system can operate correctly; characterized in that: said maximum clock frequency comprises the frequency immediately previous to the one identified as being one at which said system does not operate correctly; and in that a timing monitor is provided for determining whether or not said system can operate within system timing constraints at each frequency, thereby indicating whether or not said system operates correctly at the respective frequency.

    Abstract translation: 一种确定数字处理系统可操作的最大最佳时钟频率的方法，所述方法包括以下步骤：产生初始频率的时钟信号; 以逐步的方式增加所述频率并且确定所述系统的操作，每个频率选择一个频率，直到识别出所述处理器不正确地操作的时钟频率; 并且识别所述系统可以正确地操作的最大时钟频率; 其特征在于：所述最大时钟频率包括紧邻所述系统未正确操作的频率之前的频率; 并且提供了一种定时监视器，用于确定所述系统是否可以在每个频率的系统定时约束内操作，从而指示所述系统是否在相应频率下正确地操作。

    PHASED OFFLOADING OF CONTENT INFORMATION
    22.
    发明申请
    PHASED OFFLOADING OF CONTENT INFORMATION 审中-公开
    相关内容信息的卸载

    公开(公告)号：WO2005029360A1

    公开(公告)日：2005-03-31

    申请号：PCT/IB2004/051745

    申请日：2004-09-13

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco ,  BARBIERI, Mauro

    Inventor： PESSOLANO, Francesco ,  BARBIERI, Mauro

    IPC: G06F17/30

    CPC classification number: G06F17/30902

    Abstract: A user of a mobile client requests electronic content information for being downloaded via a data network. The client first receives a semantically summarized version of the requested content information. If the downloading is prematurely interrupted, the user has at least a meaningful summary available.

    Abstract translation: 移动客户端的用户请求通过数据网络下载电子内容信息。 客户端首先接收所请求内容信息的语义汇总版本。 如果下载过早中断，用户至少有一个有意义的摘要可用。

    TIMING CLOSURE MONITORING CIRCUIT AND METHOD
    23.
    发明申请
    TIMING CLOSURE MONITORING CIRCUIT AND METHOD 审中-公开
    定时闭合监测电路及方法

    公开(公告)号：WO2004111667A1

    公开(公告)日：2004-12-23

    申请号：PCT/IB2004/050823

    申请日：2004-06-02

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco ,  THEUNISSEN, Bob, B., A.

    Inventor： PESSOLANO, Francesco ,  THEUNISSEN, Bob, B., A.

    IPC: G01R31/30

    CPC classification number: G01R31/31727 ,  G01R31/31725 ,  G01R31/31922 ,  G06F11/24

    Abstract: An integrated circuit 1 comprises a timing closure monitoring circuit 2. The timing closure monitoring circuit 2 comprises a duplicate path 19, having the same characteristics as a logic path 3 being monitored. The duplicate path 19 receives a pulsed reference signal 23 from a reference generating unit (RGU) 24. The pulsed reference signal 23 is synchronized with the clock signal 13, and passed through the duplicate path 19 to a reference checking unit (RCU) 25. In a normal mode of operation in which timing closure is guaranteed, the clock signal 13 will sample the pulsed reference signal 23, such that no interrupt signal is generated on the interrupt line 33. However, in the situation where the reference check unit 25 is clocked by the clock signal 13 prior to the pulsed reference signal 23 being received via the duplicate path 19, an interrupt signal is generated on the interrupt line 33, indicating that timing closure cannot be guaranteed.

    Abstract translation: 集成电路1包括定时闭合监视电路2.定时闭合监视电路2包括具有与被监控的逻辑路径3相同的特征的复制路径19。 复制路径19从参考生成单元（RGU）24接收脉冲参考信号23.脉冲参考信号23与时钟信号13同步，并通过复制路径19到参考检查单元（RCU）25。 在保证定时闭合的正常操作模式中，时钟信号13将采样脉冲参考信号23，使得在中断线33上不产生中断信号。然而，在参考检查单元25为 在通过复制路径19接收到脉冲参考信号23之前由时钟信号13计时，在中断线33上产生中断信号，表明无法保证定时关闭。

    ACTIVITY PROFILING FOR CONTROLLING INTEGRATED CIRCUIT OPERATION
    25.
    发明申请
    ACTIVITY PROFILING FOR CONTROLLING INTEGRATED CIRCUIT OPERATION 审中-公开
    用于控制集成电路操作的活动分析

    公开(公告)号：WO2004097689A1

    公开(公告)日：2004-11-11

    申请号：PCT/IB2004/050514

    申请日：2004-04-26

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco ,  PINEDA DE GYVEZ, Jose, D., J. ,  KRISHNAN, Rohini

    Inventor： PESSOLANO, Francesco ,  PINEDA DE GYVEZ, Jose, D., J. ,  KRISHNAN, Rohini

    IPC: G06F17/50

    CPC classification number: G06F1/3203 ,  G06F1/32

    Abstract: Apparatus and method for controlling integrated circuit operation, comprising software means for generating simulated or estimated activity, and hardware control means for monitoring real-time activity of the integrated circuit. For every clock period the hardware retrieves (at step 200) the activity estimation for the next operation. This value may be adjusted (at step 202) with an offset previously calculated which is intended to correct the estimation so as to correspond with real, monitored activity of the chip. This value (i.e. the estimation value with the offset) is used (at step 204) to control the chip (module) as it is considered to better represent the activity of the next operation. When the next operation is being executed, the activity of the chip is also measured (at step 206), and this value is then used to generate an average of the activity of all previous operations (step 208). The measured average and the estimated one are compared (at step 210) so as to determine how accurate the estimate was, and an adjusting offset may be generated (at step 212) which is the difference between the two compared values.

    Abstract translation: 用于控制集成电路操作的装置和方法，包括用于产生模拟或估计的活动的软件装置，以及用于监视集成电路的实时活动的硬件控制装置。 对于每个时钟周期，硬件检索（在步骤200）用于下一个操作的活动估计。 可以用先前计算的偏移来调整该值（在步骤202），该偏移旨在校正估计，以便与芯片的真实的，监视的活动相对应。 使用该值（即具有偏移的估计值）（在步骤204）来控制芯片（模块），因为它被认为更好地表示下一个操作的活动。 当执行下一个操作时，还测量芯片的活动（在步骤206），然后使用该值来产生所有先前操作的活动的平均值（步骤208）。 将测量的平均值和估计的平均值和估计的平均值进行比较（在步骤210），以便确定估计的准确度，并且可以生成调整偏移（在步骤212），其是两个比较值之间的差。

    METHOD AND APPARATUS FOR TUNING A DIGITAL SYSTEM
    26.
    发明申请
    METHOD AND APPARATUS FOR TUNING A DIGITAL SYSTEM 审中-公开
    用于调整数字系统的方法和装置

    公开(公告)号：WO2006075287A3

    公开(公告)日：2007-04-05

    申请号：PCT/IB2006050083

    申请日：2006-01-10

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J ,  HEIJLIGERS MARCUS J M

    Inventor： PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J ,  HEIJLIGERS MARCUS J M

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A digital system 1 comprises receiving means (5) for receiving one or more performance indicators or parameters from software (6) controlling the execution of an application (3). Based on the performance indicators received by the receiving means (5), a tuning circuit (7) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system (1). In addition, pipeline configuration means (8) are provided for configuring the pipeline of the digital system (1) based on a pipeline depth determined by selecting means (10). The selecting means (10) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.

    Abstract translation: 数字系统1包括用于从控制应用程序（3）的执行的软件（6）接收一个或多个性能指示符或参数的接收装置（5）。 基于由接收装置（5）接收的性能指标，提供调谐电路（7），用于调谐数字系统的频率（f），电源电压（Vdd）和/或晶体管阈值电压（Vb） 1）。 此外，提供管线配置装置（8），用于基于由选择装置（10）确定的流水线深度来配置数字系统（1）的流水线。 选择装置（10）被配置为基于频率（f），电源电压（Vdd），晶体管阈值电压（Vb）以及根据应用是否需要最大吞吐量或最小等待时间来选择流水线深度（Pd）。

    CLOSED-LOOP CONTROL FOR PERFORMANCE TUNING
    27.
    发明申请
    CLOSED-LOOP CONTROL FOR PERFORMANCE TUNING 审中-公开
    闭环控制性能调节

    公开(公告)号：WO2005124516A3

    公开(公告)日：2006-08-03

    申请号：PCT/IB2005051894

    申请日：2005-06-09

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J

    Inventor： PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J

    IPC: G06F1/28 ,  G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.

    Abstract translation: 本发明涉及一种用于响应于监视的性能指示器来控制集成电路的性能的方法和电路装置，其中基于所述性能指标来控制集成电路的电源。 如果检查结果不在预定范围内，则监控受控电源的噪声电平和在所述集成电路中产生的时钟频率中的至少一个，并且将相应的控制信号反馈到控制功能。 因此，可以实现简单且易于扩展的自动适应过程变化。

    A DELAY CIRCUIT
    28.
    发明申请
    A DELAY CIRCUIT 审中-公开
    延时电路

    公开(公告)号：WO2005074134A1

    公开(公告)日：2005-08-11

    申请号：PCT/IB2005/050227

    申请日：2005-01-19

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco

    Inventor： PESSOLANO, Francesco

    IPC: H03K5/13

    CPC classification number: H03K5/133 ,  H03K5/06 ,  H03K2005/00156

    Abstract: A delay circuit comprising first and second transistors (Ml, M2), the gate of each of which being coupled to the input (or "PRE") signal. The drain of the second transistor (M2) is connected to the supply voltage V D D and its source is coupling to the drain of the first transistor (M1). A third transistor (MO) is provided, the input signal (PRE) being coupled to its gate via an inverter (10). The drain of transistor (MO) is connected at a point between the source of transistor (M2) and the drain of transistor (M I), and the source of transistor (MO) is connected to ground. A capacitor (CO) is connected between the source of transistor (M1) and ground, and a buffer (20) is provided at the output (TIMER). The function of this arrangement is to propagate with delay the transitions from the PRE signal to the TIMER signal. The rising transition is propagated very fast, the speed of propagation being equal to the charging time of capacitor (CO) through the two conducting transistors (M1, M2). The falling transition, on the other hand, is propagated with a large delay as it is equal to the charging time of the capacitor through a conducting transistor (MO) and a transistor in sub-threshold (Ml).

    Abstract translation: 一种包括第一和第二晶体管（M1，M2）的延迟电路，每个晶体管的栅极耦合到输入（或“PRE”）信号。 第二晶体管（M2）的漏极连接到电源电压VDD，其源极耦合到第一晶体管（M1）的漏极。 提供第三晶体管（MO），所述输入信号（PRE）经由逆变器（10）耦合到其栅极。 晶体管（MO）的漏极连接在晶体管（M2）的源极和晶体管（M I）的漏极之间，晶体管（MO）的源极接地。 电容器（CO）连接在晶体管（M1）的源极和地之间，并且在输出端（TIMER）提供缓冲器（20）。 这种布置的功能是延迟传播从PRE信号到TIMER信号的转换。 上升的转变传播非常快，传播速度等于通过两个导电晶体管（M1，M2）的电容器（CO）的充电时间。 另一方面，下降转换通过导通晶体管（MO）和次阈值（M1）中的晶体管等于电容器的充电时间，以较大的延迟被传播。

    ELECTRONIC CIRCUIT DEVICE FOR CRYPTOGRAPHIC APPLICATIONS
    30.
    发明申请
    ELECTRONIC CIRCUIT DEVICE FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
    电子电路装置的密码应用

    公开(公告)号：WO2004095366A8

    公开(公告)日：2004-12-09

    申请号：PCT/IB2004050478

    申请日：2004-04-21

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

    Inventor： PESSOLANO FRANCESCO

    IPC: G06K19/073 ,  H04L9/06 ,  G07F7/10

    CPC classification number: G06K19/073 ,  G06K19/07363 ,  H04L9/003 ,  H04L2209/125

    Abstract: The electronic circuit executes operations dependent on secret information. Power supply current dependency on the secret information is cloaked by drawing additional power supply current. A plurality of processing circuits (102, 106) executes respective parts of the operations dependent on the secret information. An activity monitor circuit (12a, b, 14), coupled to receive pairs of processing signals coming into and out of respective ones of the processing circuits, derive activity information from each pair of processing signals. The activity monitoring circuit (12a, b, 14) generates a combined activity signal indicative of a sum of power supply currents that will be consumed by the processing circuits (102, 106) dependent on the processing signals. A current drawing circuit connected to the power supply connections is controlled by the activity monitor circuit (12a, b, 14) to draw a cloaking current controlled by the combined activity signal, so that power supply current variations dependent on the secret information are cloaked in a sum of the cloaking current and current drawn by the processing circuits (102, 106).

    Abstract translation: 电子电路执行取决于秘密信息的操作。 通过汲取额外的电源电流掩盖电源电流对秘密信息的依赖。 多个处理电路（102,106）执行取决于秘密信息的操作的各个部分。 被耦合以接收进出各个处理电路的处理信号对的活动监视电路（12a，b，14）从每对处理信号中导出活动信息。 活动监视电路（12a，b，14）根据处理信号产生指示将由处理电路（102,106）消耗的电源电流之和的组合活动信号。 连接到电源连接的电流绘图电路由活动监视电路（12a，b，14）控制以绘制由组合活动信号控制的隐藏电流，使得取决于秘密信息的电源电流变化隐藏在 由处理电路（102,106）汲取的隐形电流和电流的总和。

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