公开(公告)号：WO2006075287A2

公开(公告)日：2006-07-20

申请号：PCT/IB2006/050083

申请日：2006-01-10

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco ,  MEIJER, Rinze, I., M., P. ,  PINEDA DE GYVEZ, Jose, D., J. ,  HEIJLIGERS, Marcus, J., M.

Inventor： PESSOLANO, Francesco ,  MEIJER, Rinze, I., M., P. ,  PINEDA DE GYVEZ, Jose, D., J. ,  HEIJLIGERS, Marcus, J., M.

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A digital system 1 comprises receiving means (5) for receiving one or more performance indicators or parameters from software (6) controlling the execution of an application (3). Based on the performance indicators received by the receiving means (5), a tuning circuit (7) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system (1). In addition, pipeline configuration means (8) are provided for configuring the pipeline of the digital system (1) based on a pipeline depth determined by selecting means (10). The selecting means (10) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.

Abstract translation: 数字系统1包括用于从控制应用程序（3）的执行的软件（6）接收一个或多个性能指示符或参数的接收装置（5）。 基于由接收装置（5）接收的性能指标，提供调谐电路（7），用于调谐数字系统的频率（f），电源电压（Vdd）和/或晶体管阈值电压（Vb） 1）。 此外，提供管线配置装置（8），用于基于由选择装置（10）确定的流水线深度来配置数字系统（1）的流水线。 选择装置（10）被配置为基于频率（f），电源电压（Vdd），晶体管阈值电压（Vb）以及根据应用是否需要最大吞吐量或最小等待时间来选择流水线深度（Pd）。

公开(公告)号：WO2005073828A3

公开(公告)日：2005-08-11

申请号：PCT/IB2005/050234

申请日：2005-01-20

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco

Inventor： PESSOLANO, Francesco

IPC: G06F1/00

Abstract: A method of determining a maximum optimum clock frequency at which a digital processing system can operate, the method comprising the steps of: generating a clock signal at an initial frequency; increasing said frequency in a step-wise manner and determining the operation of said system each of a selected number of frequencies, until a clock frequency is identified at which said processor does not operate correctly; and identifying a maximum clock frequency at which said system can operate correctly; characterized in that: said maximum clock frequency comprises the frequency immediately previous to the one identified as being one at which said system does not operate correctly; and in that a timing monitor is provided for determining whether or not said system can operate within system timing constraints at each frequency, thereby indicating whether or not said system operates correctly at the respective frequency.

公开(公告)号：WO2004025838A1

公开(公告)日：2004-03-25

申请号：PCT/IB2003/003496

申请日：2003-08-06

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco ,  VAN DIJK, Victor, E., S.

Inventor： PESSOLANO, Francesco ,  VAN DIJK, Victor, E., S.

IPC: H03M5/02

CPC classification number: H04L25/0266 ,  G01R31/318538 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for coding information in an electronic circuit and an electronic circuit for coding information, said circuit comprising at least two electrically coupled signal paths (X0, X1). The invention is based on the idea that cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first path (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0), an output signal (X) having a second logic value is produced.

Abstract translation: 本发明涉及一种用于对电子电路中的信息进行编码的方法和用于编码信息的电子电路，所述电路包括至少两个电耦合信号路径（X0，X1）。 本发明基于以下思想：可以利用两个电耦合信号路径（X0，X1）之间的串扰进行逻辑运算。 信号在两个信号路径（X0，X1）上以上升或下降转换的形式传播。 两个路径（X0，X1）上的转换之间的相对延迟决定了要产生的输出信号（X）的逻辑值。 如果第一路径（X0）上的信号比第二路径（X1）上的信号传播得更快，则产生具有第一逻辑值的输出信号（X）。 如果第二路径（X1）上的信号比第一路径（X0）上的信号传播得更快，则产生具有第二逻辑值的输出信号（X）。

公开(公告)号：WO2006100623A1

公开(公告)日：2006-09-28

申请号：PCT/IB2006/050793

申请日：2006-03-14

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  BARBIERI, Mauro ,  PESSOLANO, Francesco ,  NOTARI, Andrea

Inventor： BARBIERI, Mauro ,  PESSOLANO, Francesco ,  NOTARI, Andrea

IPC: G06T11/60 ,  G06T5/00

CPC classification number: G06T11/60 ,  G06T7/97

Abstract: Two or more digital images are combined. Three digital images are taken, Image blocks (Bi(x,y)) of a first image are matched to image blocks (B2(x,y)) of a second image, and for matching blocks a block difference (MAD12) is determined. If this block difference is below a threshold, the relevant image block of the first image is assigned to be an image block (Bg(x,y)) of the composite image. The remaining image blocks of the first image are matched to image blocks (B3 (x,y)) of the third image, and a further block difference (MAD13) is determined. If said further block difference is below a threshold, the relevant image block of the second image is assigned to be an image block of the composite image, otherwise the relevant image block of the first image is assigned to be an image block of the composite image.

Abstract translation: 组合两个或多个数字图像。 拍摄三个数字图像，第一图像的图像块（Bi（x，y））与第二图像的图像块（B2（x，y））匹配，并且为了匹配块，确定块差（MAD12） 。 如果该块差异低于阈值，则将第一图像的相关图像块分配为合成图像的图像块（Bg（x，y））。 第一图像的剩余图像块与第三图像的图像块（B3（x，y））匹配，并且确定另一块差异（MAD13）。 如果所述另外的块差异低于阈值，则将第二图像的相关图像块分配为合成图像的图像块，否则将第一图像的相关图像块分配为合成图像的图像块 。

公开(公告)号：WO2005088421A3

公开(公告)日：2006-03-16

申请号：PCT/IB2005050713

申请日：2005-02-28

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G06F1/06 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/06

Abstract: A mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change) without spurious signals or glitches being created on the clock output line. A electronic device according to an exemplary embodiment, comprises a multiplexer (10) having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer (10) via a set of generic combinatorial delay elements (12) and the multiplexer output id fed to the output (Out) via an inverter (14). The element further comprises a D-type flip-flop (16) having as its "D" input a programming signal (Fk), and the two outputs "Q" and "Qn" from the D-type flip-flop provided respective drive signals to the multiplexer (10). The delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal (Fk), which is synchronized on the rising edge of the local clock (sync_ck).

Abstract translation: 一种用于产生集成电路或其一部分的时钟信号的机制，使得其频率可以在时钟输出线上不产生杂散信号或毛刺的情况下连续地（即逐渐变化的频率）安全地改变。 根据示例性实施例的电子设备包括具有两个输入信号的多路复用器（10），其中第二个是第一个的延迟版本，通过一组通用组合延迟将输入馈送到多路复用器（10）而产生 元件（12）和通过反相器（14）馈送到输出（Out）的多路复用器输出id。 该元件还包括具有作为其“D”输入编程信号（Fk）的D型触发器（16），并且提供来自D型触发器的两个输出“Q”和“Qn” 信号到多路复用器（10）。 输出信号（Out）相对于输入信号（In）的延迟取决于在本地时钟（sync_ck）的上升沿同步的编程信号（Fk）的值。

公开(公告)号：WO2005125012A1

公开(公告)日：2005-12-29

申请号：PCT/IB2005/051892

申请日：2005-06-09

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  MEIJER, Rinze, I., M., P. ,  PESSOLANO, Francesco ,  PINEDA DE GYVEZ, Jose, D., J.

Inventor： MEIJER, Rinze, I., M., P. ,  PESSOLANO, Francesco ,  PINEDA DE GYVEZ, Jose, D., J.

IPC: H03K19/00

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.

Abstract translation: 本发明涉及一种用于控制集成电路中的电源的电路装置和方法，其中监视至少一个电隔离电路区域（10）的至少一个工作参数，并且可变电阻器装置的电导率被局部控制 以便基于所述至少一个被监视的工作参数单独地调节所述至少两个电隔离电路区域（10）中的每一个的电源。 因此，可以提供具有低面积开销的快速和简单的控制功能。

公开(公告)号：WO2005124516A2

公开(公告)日：2005-12-29

申请号：PCT/IB2005/051894

申请日：2005-06-09

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco ,  MEIJER, Rinze, I., M., P. ,  PINEDA DE GYVEZ, Jose, D., J.

Inventor： PESSOLANO, Francesco ,  MEIJER, Rinze, I., M., P. ,  PINEDA DE GYVEZ, Jose, D., J.

IPC: G06F1/28

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.

Abstract translation: 本发明涉及一种用于响应于监视的性能指示器来控制集成电路的性能的方法和电路装置，其中基于所述性能指标来控制集成电路的电源。 如果检查结果不在预定范围内，则监视受控电源的噪声电平和在所述集成电路中产生的时钟频率中的至少一个，并且将相应的控制信号反馈到控制功能。 因此，可以实现简单且易于扩展的自动适应过程变化。

公开(公告)号：WO2005104233A1

公开(公告)日：2005-11-03

申请号：PCT/IB2005/051268

申请日：2005-04-19

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PINEDA DE GYVEZ, Jose, D., J. ,  PESSOLANO, Francesco ,  RAO, Kiran, B., R. ,  MEIJER, Rinze, I., M., P. ,  RIUS VAZQUEZ, Josep

Inventor： PINEDA DE GYVEZ, Jose, D., J. ,  PESSOLANO, Francesco ,  RAO, Kiran, B., R. ,  MEIJER, Rinze, I., M., P. ,  RIUS VAZQUEZ, Josep

IPC: H01L27/118

CPC classification number: H01L27/0211

Abstract: A header transistor (3) and footer transistor (5) provide a virtual power supply for a core (1) on an integrated circuit. The header transistor (3) and/or footer transistor (5) are partitioned into a number of smaller transistors. For example, the header transistor (3) is partitioned into a first segment 3a and a second segment 3b, while the footer transistor (5) is partitioned into a first segment 5a and a second segment 5b. The combined width of each segment 3a/3b and 5a/5b will be the same as a single header/footer transistor (3, 5) of the prior art. However, the individual widths of each segment 3a, 3b, 5a and 5b will be smaller, thereby improving the layout of the header/footer transistors (3, 5) in the integrated circuit design. The header transistor( 3) and the footer transistor (5) are uniformly arranged around the core (1). This has the advantage of enabling the power to be uniformly distributed to the core, thereby avoiding localized temperature rises.

Abstract translation: 标头晶体管（3）和页脚晶体管（5）为集成电路上的核心（1）提供虚拟电源。 标头晶体管（3）和/或脚底晶体管（5）被划分成多个较小的晶体管。 例如，头部晶体管（3）被分割成第一部分3a和第二部分3b，而脚踏晶体管（5）被分成第一部分5a和第二部分5b。 每个区段3a / 3b和5a / 5b的组合宽度将与现有技术的单个页眉/页脚晶体管（3,5）相同。 然而，每个段3a，3b，5a和5b的单独宽度将较小，从而改善了集成电路设计中的标题/页脚晶体管（3,5）的布局。 标头晶体管（3）和脚踏晶体管（5）均匀地布置在芯（1）周围。 这具有使功率均匀分布到芯体的优点，从而避免局部温度升高。

公开(公告)号：WO2004095366A1

公开(公告)日：2004-11-04

申请号：PCT/IB2004/050478

申请日：2004-04-21

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PESSOLANO, Francesco

Inventor： PESSOLANO, Francesco

IPC: G06K19/073

CPC classification number: G06K19/073 ,  G06K19/07363 ,  H04L9/003 ,  H04L2209/125

Abstract: The electronic circuit executes operations dependent on secret information. Power supply current dependency on the secret information is cloaked by drawing additional power supply current. A plurality of processing circuits (102, 106) executes respective parts of the operations dependent on the secret information. An activity monitor circuit (12a, b, 14), coupled to receive pairs of processing signals coming into and out of respective ones of the processing circuits, derive activity information from each pair of processing signals. The activity monitoring circuit (12a, b, 14) generates a combined activity signal indicative of a sum of power supply currents that will be consumed by the processing circuits (102, 106) dependent on the processing signals. A current drawing circuit connected to the power supply connections is controlled by the activity monitor circuit (12a, b, 14) to draw a cloaking current controlled by the combined activity signal, so that power supply current variations dependent on the secret information are cloaked in a sum of the cloaking current and current drawn by the processing circuits (102, 106).

Abstract translation: 电子电路根据秘密信息执行操作。 通过绘制额外的电源电流来掩盖电源电流对秘密信息的依赖。 多个处理电路（102,106）根据秘密信息执行操作的各部分。 耦合到接收进入和离开各个处理电路的处理信号对的活动监视电路（12a，b，14）从每对处理信号中导出活动信息。 活动监视电路（12a，b，14）根据处理信号产生表示由处理电路（102,106）消耗的电源电流之和的组合活动信号。 连接到电源连接的电流绘制电路由活动监视电路（12a，b，14）控制，以画出由组合的活动信号控制的隐形电流，使得依赖于秘密信息的电源电流变化被隐藏 由处理电路（102,106）画出的掩蔽电流和电流的总和。

公开(公告)号：WO2006097872A2

公开(公告)日：2006-09-21

申请号：PCT/IB2006050744

申请日：2006-03-09

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO ,  BARBIERI MAURO

Inventor： PESSOLANO FRANCESCO ,  BARBIERI MAURO

IPC: G11B20/10

CPC classification number: G11B20/10527 ,  G11B2020/10722

Abstract: The content reproduction system of the invention comprises storage means (3) for storing content, reproduction means (5) for reproducing the content, a buffer (7) coupled between the storage means and the reproduction means, a motion sensor (9) for sensing motion, and control circuitry (11) operative to configure the buffer's (7) size in dependence on the sensed motion. The method of the invention comprises the steps of reading content from a storage means into a buffer, reproducing content from the buffer using a reproduction means, sensing motion using a motion sensor, and configuring the buffer's size in dependence on the sensed motion.

Abstract translation: 本发明的内容再现系统包括用于存储内容的存储装置（3），用于再现内容的再现装置（5），耦合在存储装置和再现装置之间的缓冲器（7），用于感测的运动传感器 运动和控制电路（11），用于根据感测到的运动来配置缓冲器（7）的尺寸。 本发明的方法包括以下步骤：将内容从存储装置读入缓冲器，使用再现装置从缓冲器再现内容，使用运动传感器感测运动，以及根据所感测到的运动来配置缓冲器的大小。