公开(公告)号：WO2019005171A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040517

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： NAIR, Vijay K. ,  RAORANE, Digvijay A.

IPC: H01L23/31 ,  H01L23/552

Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

公开(公告)号：WO2017172059A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/017226

申请日：2017-02-09

Applicant: INTEL CORPORATION

Inventor： DOGIAMIS, Georgios C. ,  EID, Feras ,  ELSHERBINI, Adel A. ,  NAIR, Vijay K. ,  KAMGAING, Telesphor ,  RAO, Valluri R. ,  SWAN, Johanna M.

IPC: H01H57/00 ,  H01L41/09 ,  H01L41/047 ,  H01L41/083

CPC classification number: B81C1/0015 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04

Abstract: Embodiments of the invention include a switching device that includes an electrode, a piezoelectric material coupled to the electrode, and a movable structure (e.g., cantilever, beam) coupled to the piezoelectric material. The movable structure includes a first end coupled to an anchor of a package substrate having organic layers and a second released end positioned within a cavity of the package substrate.

Abstract translation: 本发明的实施例包括开关装置，其包括电极，耦合到电极的压电材料以及耦合到压电材料的可移动结构（例如，悬臂梁）。 可移动结构包括耦合到具有有机层的封装衬底的锚的第一端和位于封装衬底的空腔内的第二释放端。

公开(公告)号：WO2017171807A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025335

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： NAIR, Vijay K. ,  RAORANE, Digvijay

IPC: H01L23/552 ,  H01L23/48

Abstract: A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.

Abstract translation: 这里描述了使用金属层和通孔的电磁屏蔽的半导体封装。 在一个示例中，封装包括具有正面和背面的硅衬底，正面包括有源电路和用于附接到衬底的触点阵列，在裸片背面上的金属化层以屏蔽有源电路 来自穿过背面的干扰，以及多个硅通孔，所述多个硅通孔在一端耦合到背面金属化部，并且在另一端耦合到焊盘阵列的正面焊盘，以屏蔽有源电路免受通过管芯的侧面的干扰