公开(公告)号：WO2006116257A3

公开(公告)日：2006-11-02

申请号：PCT/US2006/015390

申请日：2006-04-24

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William, C.

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William, C.

IPC: G06F9/38

Abstract: A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.

公开(公告)号：WO2006099584A2

公开(公告)日：2006-09-21

申请号：PCT/US2006/009782

申请日：2006-03-14

Applicant: QUALCOMM INCORPORATED ,  JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ANDERSON, William C.

Inventor： JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ANDERSON, William C.

IPC: G06F9/38

CPC classification number: G06F9/3851

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. A multithreaded processor processes a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor and predetermines a triggering event for the multithreaded processor to switch from a first thread to a second thread. The triggering event is variably and dynamically determined to optimize multithreaded processor performance. The triggering event may be a dynamically determined number of processor cycles, the number being determined to optimize the performance of the multithreaded processor, or a variably and dynamically determined event, such as a cache or instruction miss.

Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 多线程处理器处理通过与多线程处理器相关联的多个处理器管线操作的多个线程，并且预先确定用于多线程处理器从第一线程切换到第二线程的触发事件。 触发事件是可变和动态的，以优化多线程处理器性能。 触发事件可以是动态确定的处理器周期数，被确定为优化多线程处理器的性能的数量，或可变和动态确定的事件，例如高速缓存或指令未命中。

公开(公告)号：WO2022051422A1

公开(公告)日：2022-03-10

申请号：PCT/US2021/048745

申请日：2021-09-01

Applicant: QUALCOMM INCORPORATED

Inventor： WOLFE, Jonathan Dewitt ,  PLONDKE, Erich

IPC: G06F9/48 ,  G06F8/41

Abstract: Certain aspects of the present disclosure provide techniques for generating execution schedules, comprising receiving a data flow graph for a process, where data flow graph comprises a plurality of nodes and a plurality of edge; generating a topological ordering for the data flow graph based at least in part on memory utilization of the process; generating a first modified topological ordering by inserting, into the topological ordering, one or more new nodes corresponding to memory access based on a predefined memory capacity; allocating units of memory in the memory based on the first modified topological ordering; and generating a second modified topological ordering by rearranging one or more nodes in the first modified topological ordering, where the second modified topological ordering enables increased parallel utilization of a plurality of hardware components.

公开(公告)号：WO2019221976A1

公开(公告)日：2019-11-21

申请号：PCT/US2019/031129

申请日：2019-05-07

Applicant: QUALCOMM INCORPORATED

Inventor： MAHURIN, Eric Wayne ,  PLONDKE, Erich ,  HOYLE, David

IPC: G06F9/30

Abstract: A processor includes a vector register configured to load data responsive to a special purpose load instruction. The processor also includes circuitry configured to replicate a selected sub-vector value from the vector register.

公开(公告)号：WO2019125835A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/065034

申请日：2018-12-11

Applicant: QUALCOMM INCORPORATED

Inventor： DANYSH, Albert ,  PLONDKE, Erich ,  MAHURIN, Eric

IPC: G06F7/523 ,  G06F7/53

CPC classification number: G06F7/4876 ,  G06F7/485 ,  G06F7/523 ,  G06F7/5324

Abstract: A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

公开(公告)号：WO2009158370A2

公开(公告)日：2009-12-30

申请号：PCT/US2009/048370

申请日：2009-06-24

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  WANG, Lin ,  VENKUMAHANTI, Suresh, K.

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  WANG, Lin ,  VENKUMAHANTI, Suresh, K.

IPC: G06F9/445

CPC classification number: G06F8/4452 ,  G06F9/30072 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

Abstract: Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.

Abstract translation: 公开了回路控制系统和方法。 在特定实施例中，硬件回路控制逻辑电路包括检测单元以检测程序循环的循环指示符的结束。 硬件回路控制逻辑电路还包括递减单元，用于递减循环计数并递减谓词触发计数器。 硬件循环控制逻辑电路还包括比较单元，用于将谓词触发计数器与参考值进行比较，以确定何时设置谓词值。

公开(公告)号：WO2008016856A1

公开(公告)日：2008-02-07

申请号：PCT/US2007/074639

申请日：2007-07-27

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ZENG, Mao

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  ZENG, Mao

IPC: G06F9/302 ,  G06F9/308 ,  G06F9/312

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30018

Abstract: A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a processing unit. The instruction includes a shifting bit value indicating the bit amount for a right shift operation and is subsequently executed to shift data within the source register unit to the right by an encoded bit value, calculated by subtracting a single bit from the shifting bit value contained within the instruction. A predetermined bit extension is further inserted within the vacated bit positions adjacent to the shifted data. Subsequently, an addition operation is performed on the shifted data and a unitary integer value is added to the shifted data to obtain resulting data. Finally, the resulting data is further shifted to the right by a single bit value and a predetermined bit extension is inserted within the vacated bit position to obtain the final rounded data results to be stored within a destination register unit.

Abstract translation: 描述了在执行单个指令期间在微处理器（例如数字信号处理器）内执行移位和舍入操作的方法和系统。 在处理单元内接收用于在寄存器堆结构的源寄存器单元内移位和舍入数据的指令。 该指令包括指示右移位操作的位量的移位位值，并且随后被执行以将源寄存器单元内的数据向右移位编码位值，该编码位值通过从包含在其中的移位位值中减去单个位而被计算 指示。 进一步将预定比特扩展插入与移位数据相邻的空闲比特位置。 随后，对移位的数据执行相加操作，并将一个整数值加到移位数据上，以获得结果数据。 最后，所得到的数据进一步向右移位一个位值，并且将预定的位扩展插入到空出的位位置中，以获得存储在目的地寄存器单元内的最终舍入数据结果。

公开(公告)号：WO2008008999A1

公开(公告)日：2008-01-17

申请号：PCT/US2007/073535

申请日：2007-07-13

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  JANJANAM, Vijaya Kumar

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  JANJANAM, Vijaya Kumar

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.

Abstract translation: 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，获取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。

公开(公告)号：WO2007002415A1

公开(公告)日：2007-01-04

申请号：PCT/US2006/024500

申请日：2006-06-23

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich ,  ANDERSON, William, C. ,  CONDRESCU, Lucian

Inventor： PLONDKE, Erich ,  ANDERSON, William, C. ,  CONDRESCU, Lucian

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  G06F12/1027 ,  Y02D10/13 ,  Y02D10/24

Abstract: A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.

Abstract translation: 共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新​​启用异常和可选中断，解决原因 异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。

公开(公告)号：WO2006110906A2

公开(公告)日：2006-10-19

申请号：PCT/US2006/014174

申请日：2006-04-11

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William, C. ,  SIMPSON, Taylor

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William, C. ,  SIMPSON, Taylor

CPC classification number: H04M1/72522 ,  G06F9/3012 ,  G06F9/3885 ,  H04M1/2535 ,  H04M2250/02

Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.

Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 音序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元和响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。