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    CHANNEL SELECT FILTER APPARATUS AND METHOD
    31.
    发明申请
    CHANNEL SELECT FILTER APPARATUS AND METHOD 审中-公开
    通道选择滤波器和方法

    公开(公告)号：WO2010088293A2

    公开(公告)日：2010-08-05

    申请号：PCT/US2010022266

    申请日：2010-01-27

    Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN

    Inventor： MALLINSON ANDREW MARTIN

    IPC: H03H17/00

    CPC classification number: H03H17/0248 ,  B60N2/002 ,  H03H15/00 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

    Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non- radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital- to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.

    Abstract translation: 描述通道选择滤波器电路。 一个电路实现了一个乘法元件和数模转换器作为差分电流模式器件。 实现乘法元件和数模转换器的另一个电路，具有加权相加，在数模转换器和乘法器组合相乘后延迟。 在一个这样的电路中，基本相等的电流源幅度在电路的不同列中。 另一个具有基本相等的电流源幅度的这种电路使用非基2。 具有基本相等的电流源幅度的另一个这样的电路具有部分分割。 另一电路实现了乘法元件和数模转换器，具有部分分段，元件的加扰位分配。 如这里所述，一个这样的电路对等加权的片段进行比特分配。 另一个电路实现了具有选择性地启用重复的电流源装置的乘法元件和数模转换器。 另一电路实现了具有可变有效长度的数模转换器的乘法元件和数模转换器。 在一个这样的电路中，如本文所述，乘法器元件的一个或多个电流源被取消选择以去除乘法器元件的噪声贡献。 复合滤波电路包括一对实际有限脉冲响应滤波器电路，在当前域进行加法和减法，共享公共电阻网络以执行加权相加。 一个这样的电路还包括第二对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享第二公共电阻器网络以执行加权相加。

    DIGITAL FEEQUENCY GENERATOR
    32.
    发明申请
    DIGITAL FEEQUENCY GENERATOR 审中-公开
    数字式发电机

    公开(公告)号：WO2009089321A3

    公开(公告)日：2009-12-03

    申请号：PCT/US2009030398

    申请日：2009-01-08

    Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN

    Inventor： MALLINSON ANDREW MARTIN

    IPC: H03B28/00

    CPC classification number: H03K3/0315 ,  H03K23/004 ,  H03K23/502 ,  H03L1/00 ,  H03L1/027

    Abstract: A feed-forward control loop circuit, almost-binary counter and ring oscillator, comprising: an oscillation source; a reference frequency source having a second frequency independently generated from the oscillation source; a measurement circuit responsive to the reference source and the oscillation source; a first circuit accepting an input frequency and creating an output frequency dependent on another input; and a second circuit operating on an output of the measurement circuit and receiving a frequency input. The feed-forward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward control loop.

    Abstract translation: 一种前馈控制回路电路，几乎是二进制计数器和环形振荡器，包括：振荡源; 具有从振荡源独立产生的第二频率的参考频率源; 响应于参考源和振荡源的测量电路; 第一电路接受输入频率并产生取决于另一输入的输出频率; 以及在所述测量电路的输出上工作并接收频率输入的第二电路。 前馈控制环路产生来自第一电路的输出，参考源和频率输入足以确定前馈控制回路的输出。

    SPREAD SPECTRUM CLOCK GENERATOR HAVING AN ADJUSTABLE DELAY LINE
    37.
    发明申请
    SPREAD SPECTRUM CLOCK GENERATOR HAVING AN ADJUSTABLE DELAY LINE 审中-公开
    具有可调延时线的扩频时钟发生器

    公开(公告)号：WO2007006048A3

    公开(公告)日：2007-04-26

    申请号：PCT/US2006026560

    申请日：2006-07-06

    Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN

    Inventor： MALLINSON ANDREW MARTIN

    IPC: H04L25/00 ,  H04B1/707

    CPC classification number: H04B15/02 ,  H04B1/707 ,  H04B2215/067

    Abstract: A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.

    Abstract translation: 提供了一种用于执行扩频时钟生成的系统和方法，其中该系统包括：自调节延迟线，被配置为使用固定时钟频率来扩展固定电路的频谱;以及延迟电路，被配置为生成对延迟的调节信号 通过在每个周期增加或减去相加延迟，从而导致输出时钟频率偏移，其中偏移量与延迟的加减速率成比例。

    PROGRAMMABLE REFERENCE VOLTAGE CALIBRATION DESIGN
    38.
    发明申请
    PROGRAMMABLE REFERENCE VOLTAGE CALIBRATION DESIGN 审中-公开
    可编程参考电压校准设计

    公开(公告)号：WO2006060307A3

    公开(公告)日：2007-03-08

    申请号：PCT/US2005042884

    申请日：2005-11-25

    Applicant: ESS TECHNOLOGY INC ,  ZHANG ZHIHONG ,  LUO JIAFU

    Inventor： ZHANG ZHIHONG ,  LUO JIAFU

    IPC: G06K9/00 ,  H04N5/357

    CPC classification number: H04N5/3658

    Abstract: An apparatus and method for determining a reference value for an imaging device, having a plurality of photosensitive pixels arranged in rows and columns, and having an active data portion and at least one row of pixels outside the active data portion. The method includes operating the at least one row for a predetermined integration time, applying a first reference value to the pixels ini the at least one row, reading out at least one pixel from the at least one row to obtain a first output value, applying a second reference value to the pixels in the at least one row; reading out at least one pixel from the at least one row to obtain a second output value, determining the reference value corresponding to an intended output; and applying the determined reference value to the active data portion of the imaging device.

    Abstract translation: 一种用于确定成像装置的参考值的装置和方法，所述成像装置具有以行和列排列的多个感光像素，并且在活动数据部分的外部具有活动数据部分和至少一行像素。 该方法包括对预定积分时间操作该至少一行，将第一参考值应用于至少一行中的像素，从至少一行读出至少一个像素以获得第一输出值，应用 对所述至少一行中的像素的第二参考值; 从所述至少一行读出至少一个像素以获得第二输出值，确定对应于预期输出的参考值; 以及将确定的参考值应用于成像装置的活动数据部分。

    DUAL OUTPUT SWITCHING REGULATOR AND METHOD OF OPERATION
    39.
    发明申请
    DUAL OUTPUT SWITCHING REGULATOR AND METHOD OF OPERATION 审中-公开
    双输出开关稳压器及其运行方式

    公开(公告)号：WO2006086022A2

    公开(公告)日：2006-08-17

    申请号：PCT/US2005/038616

    申请日：2005-10-26

    Applicant: ESS TECHNOLOGY, INC ,  MALLINSON, Andrew, Martin ,  FORMAN, Dustin, D.

    Inventor： MALLINSON, Andrew, Martin ,  FORMAN, Dustin, D.

    IPC: G05F1/577

    CPC classification number: H02M3/158 ,  H02M2001/009

    Abstract: A system and method of operation of a power switching circuit is provided that includes a charging switch configured to be connected to an inductor at one node and configured to receive control signals to open and close the charging switch. The circuit further includes a first channel coupled to the one node with a first channel switch, configured to supply a first channel voltage, configured to operate in one of buck mode and boost mode and configured to receive control signals to open and close the first channel switch; and a second channel coupled to the one node with a second channel switch, configured to supply a second channel voltage, configured to operate in one of buck mode and boost mode and configured to receive control signals to open and close the first channel switch.

    Abstract translation: 提供了一种功率开关电路的操作的系统和方法，其包括充电开关，其被配置为在一个节点处连接到电感器并且被配置为接收控制信号以打开和关闭充电开关。 该电路还包括与第一通道耦合到第一通道开关的第一通道，其被配置为提供第一通道电压，其被配置为以降压模式和升压模式之一操作并被配置为接收控制信号以打开和关闭第一通道 开关; 以及第二通道，其具有第二通道开关耦合到所述一个节点，其被配置为提供第二通道电压，其被配置为在降压模式和升压模式之一下操作并且被配置为接收控制信号以打开和关闭所述第一通道开关。

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