公开(公告)号：WO2007044190A2

公开(公告)日：2007-04-19

申请号：PCT/US2006036703

申请日：2006-09-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  RAO RAJESH A ,  MURALIDHAR RAMACHANDRAN

Inventor： MATHEW LEO ,  RAO RAJESH A ,  MURALIDHAR RAMACHANDRAN

IPC: H01L29/76 ,  H01L21/302 ,  H01L21/461 ,  H01L29/745

CPC classification number: H01L29/42368 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/32139 ,  H01L28/91 ,  H01L29/512 ,  H01L29/513

Abstract: A semiconductor device (10) includes a plurality of pillars (22) formed from a conductive material (16). The pillars are formed by using a plurality of nanocrystals (20) as a hardmask for patterning the conductive material (16). A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal (20). In one embodiment, the pillars (22) are formed from polysilicon and function as the charge storage region of a non-volatile memory cell (25) having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor (50) having an increased capacitance without increasing the surface area of an integrated circuit.

Abstract translation: 半导体器件（10）包括由导电材料（16）形成的多个支柱（22）。 柱通过使用多个纳米晶体（20）作为用于图案化导电材料（16）的硬掩模形成。 导电材料的厚度决定了支柱的高度。 同样地，柱的宽度由纳米晶体（20）的直径确定。 在一个实施例中，柱（22）由多晶硅形成并用作具有良好电荷保持和低电压操作的非易失性存储单元（25）的电荷存储区域。 在另一个实施例中，支柱由金属形成，并且作为具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器（50）的平板电极而起作用，而不增加集成电路的表面积。

公开(公告)号：WO2006104562A2

公开(公告)日：2006-10-05

申请号：PCT/US2006/003528

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  MATHEW, Leo ,  KOLAGUNTA, Venkat, R. ,  SING, David, C.

Inventor： MATHEW, Leo ,  KOLAGUNTA, Venkat, R. ,  SING, David, C.

IPC: H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/78624 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

Abstract: A method for forming a semiconductor device (10) including forming a semiconductor substrate (12); forming a gate electrode (16) over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area (42) under the gate electrode and adjacent the first side of the gate electrode, a second area (44) under the gate electrode and adjacent the second side of the gate electrode, and a third area (14) under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

Abstract translation: 一种形成半导体器件（10）的方法，包括形成半导体衬底（12）; 在所述半导体衬底上形成具有第一侧和第二侧的栅电极，以及在所述栅电极下方形成栅电介质。 所述栅极电介质具有位于所述栅电极下方且与所述栅电极的第一侧相邻的第一区域（42），所述栅电极下方的第二区域（44）和所述栅电极的第二侧相邻，以及第三区域 ）在所述第一区域和所述第二区域之间的所述栅极电极下方，其中所述第一区域比所述第二区域薄，并且所述第三区域比所述第一区域薄，并且比所述第二区域薄。

公开(公告)号：WO2005045892A3

公开(公告)日：2005-05-19

申请号：PCT/US2004/035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  MATHEW, Leo ,  MORA, Rode, R. ,  NGUYEN, Bich-Yen ,  STEPHENS, Tab, A. ,  VANDOOREN, Anne, M.

Inventor： MATHEW, Leo ,  MORA, Rode, R. ,  NGUYEN, Bich-Yen ,  STEPHENS, Tab, A. ,  VANDOOREN, Anne, M.

IPC: H01L21/00

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer.