INITIALIZING CIRCUIT AND SEMICONDUCTOR DEVICE USING THEREOF
    31.
    发明申请
    INITIALIZING CIRCUIT AND SEMICONDUCTOR DEVICE USING THEREOF 审中-公开
    使用它的初始化电路和半导体器件

    公开(公告)号:WO1992003825A1

    公开(公告)日:1992-03-05

    申请号:PCT/JP1991001143

    申请日:1991-08-28

    Abstract: An initializing circuit (20) for setting the initial state of a latching circuit (30) in a semiconductor device when switching on a power supply. The initializing circuit is provided with a sensing circuit (TR1, TR2, R, 21) which operates according to switching on the power supply and senses that the power supply voltage (Vcc) increases to a predetermined voltage, and a circuit (22) for controlling output levels which responds to a sense signal (V1) outputted from the sensing circuit and pulls up the level of the output signal (Vout) of the initializing circuit to a high potential level or pulls down it to a low potential level. After the power is interrupted and when the power is supplied again, the latching circuit (30) is fed with the output signal controlled by the circuit (22) as its power source voltage. Consequently the latching circuit can be reliably initialized, and the malfunction on restart is prevented.

    COMMUNICATION EQUIPMENT HAVING REPEAT SWITCHING FUNCTION
    32.
    发明申请
    COMMUNICATION EQUIPMENT HAVING REPEAT SWITCHING FUNCTION 审中-公开
    具有重复切换功能的通信设备

    公开(公告)号:WO1992003023A1

    公开(公告)日:1992-02-20

    申请号:PCT/JP1991001045

    申请日:1991-08-06

    Inventor: FUJITSU LIMITED

    CPC classification number: H04Q11/04

    Abstract: In a communication equipment having a transmission device (120B) connected with first and second transmission lines (L1, L2) and a switching system (110B) connected with the transmission device, the transmission device has a codec (123) and a switching section (122). When an aural signal received from the first transmission line (L1) is sent to a terminal provided in the switching system (110B), the aural signal of a low bit rate is converted by the codec (123) to the one of the bit rate which can be processed by the switching system (110B). On the other hand, when the aural signal received from the first transmission line (L1) is sent to the second transmission line (L2), it is sent out to the second transmission line (L2) via the switching section (122) without passing the codec (123), leaving it low in bit rate.

    CIRCUIT FOR EXTRACTING ASYNCHRONOUS SIGNAL
    33.
    发明申请
    CIRCUIT FOR EXTRACTING ASYNCHRONOUS SIGNAL 审中-公开
    提取异常信号的电路

    公开(公告)号:WO1992001343A1

    公开(公告)日:1992-01-23

    申请号:PCT/JP1991000900

    申请日:1991-07-04

    Inventor: FUJITSU LIMITED

    CPC classification number: H04L25/05 H04J3/076 H04L5/24

    Abstract: A circuit for extracting asynchronous signals which extracts the asynchronous signals multiplexed in a synchronous frame comprises a separating part (1) for separating a clock signal synchronized with an effective data in the asynchronous signals from them, a buffer memory (2) in which the effective data in the separated asynchronous signals is written by using the clock signal as a write clock signal, a phase synchronizing circuit (3) for generating a readout clock signal for the memory (2), and a controlling part (5) which controls the changeover of the band of a low-pass filter (4) in the circuit (3) periodically or according to the detecting signal for pointer-adjustment. Low-frequency jitters included in the readout clock signal is suppressed.

    DYNAMIC RAM IN WHICH TIMING OF END OF DATA READ OUT IS EARLIER THAN CONVENTIONAL
    35.
    发明申请
    DYNAMIC RAM IN WHICH TIMING OF END OF DATA READ OUT IS EARLIER THAN CONVENTIONAL 审中-公开
    数据读取结束时的动态RAM比传统的更早

    公开(公告)号:WO1991015852A1

    公开(公告)日:1991-10-17

    申请号:PCT/JP1991000424

    申请日:1991-03-30

    Inventor: FUJITSU LIMITED

    Abstract: A dynamic RAM comprising capacitors (C1, C2) of at least one memory cell each of which stores digital data of one bit as its terminal voltage, bit lines (BLi, B^¨B7L^¨B7i) provided in correspondence with at least one memory cell, gating means (QC1, QC2) provided in correspondence with the capacitors (C1, C2) so as to control electrical connection/disconnection of terminals of the capacitors (C1, C2) to the bit lines (BLi, B^¨B7L^¨B7i), and at least a pair of data bus lines (DB1, DB2) each of which is provided in correspondence with at least one bit line. Currents are fed always from a predetermined power supply (VCC) to the data bus lines (DB1, DB2) via respective predetermined resistors (Q3'', Q4''). Means (Q8'', Q9'') for outputting read out voltages are provided in correspondence with the respective bit lines (BLi, B^¨B7L^¨B7i). The current input terminals of the means (Q8'', Q9'') are connected to the data bus lines (DB1, DB2) corresponding to the bit lines. The means change the voltages of the data bus lines according to the voltage changes generated on the bit lines.

    SAMPLED DATA STORAGE AND EDITING SYSTEM
    36.
    发明申请
    SAMPLED DATA STORAGE AND EDITING SYSTEM 审中-公开
    采样数据存储和编辑系统

    公开(公告)号:WO1991014256A1

    公开(公告)日:1991-09-19

    申请号:PCT/JP1991000302

    申请日:1991-03-06

    Inventor: FUJITSU LIMITED

    Abstract: The present invention is a system that converts a vertical file (28) of time series data records from multiple terminals (10-14) and stored by time into a horizontal file (52) where records are organized by terminal (10-14). The user can then access the desired terminal information rapidly in the horizontal file (52) rather than having to perform an inefficient sequential search of the vertical file (28). After the terminal data is horizontally stored, the data is used to create display or print-out windows of the terminal data for many locations. Each window includes the data from a single terminal (10-14). For example, each window could include a graph of rain data for a location. The system also creates a cross reference table (76) of the addresses of the data used to create each window. When the display arrangement is altered, the data in the horizontal file (52/74) is reorganized to match the display order while only the physical addresses of the data for each terminal are changed in a new cross reference table (80).

    ULTRASONIC PROBE
    37.
    发明申请
    ULTRASONIC PROBE 审中-公开
    超声探头

    公开(公告)号:WO1991013588A1

    公开(公告)日:1991-09-19

    申请号:PCT/JP1990001374

    申请日:1990-10-25

    Inventor: FUJITSU LIMITED

    CPC classification number: B06B1/0629

    Abstract: This invention relates to an ultrasonic probe for controlling an ultrasonic beam by array oscillators and more particularly to an ultrasonic probe whose ultrasonic beam characteristics in the direction of the minor axis are improved in order to provide an ultrasonic diagnosis apparatus having high image quality. An object of the present invention is to improve the characteristics of an ultrasonic beam. The ultrasonic probe for controlling an ultrasonic beam by use of a large number of oscillators disposed in array has a composite piezoelectric device (1) as electro-acoustic transducers of the oscillator and has electrodes (2) that are fitted to the composite piezoelectric oscillators (1) and are divided in the direction of the minor axis which is orthogonal to the array direction of the large number of oscillators.

    Abstract translation: 本发明涉及一种用于通过阵列振荡器控制超声波束的超声波探头,更具体地说,涉及提供超短波短轴特性的超声波探头,以提供具有高图像质量的超声波诊断装置。 本发明的目的是提高超声波束的特性。 用于通过使用排列成阵列的大量振荡器控制超声波束的超声波探头具有作为振荡器的电声换能器的复合压电装置(1),并具有装配到复合压电振荡器的电极(2) 1),并且在与大量振荡器的阵列方向正交的短轴方向上分割。

    DEVICE FOR ADJUSTING FOCAL POINT OF AN OPTICAL PICKUP DEVICE
    38.
    发明申请
    DEVICE FOR ADJUSTING FOCAL POINT OF AN OPTICAL PICKUP DEVICE 审中-公开
    用于调整光学拾取器件的焦点的器件

    公开(公告)号:WO1991006097A1

    公开(公告)日:1991-05-02

    申请号:PCT/JP1990001325

    申请日:1990-10-15

    Abstract: A device for adjusting the focal point of an optical pickup device in which the light reflected by a recording medium is focused at points of two systems using an optical branching filter, first and second light detectors are disposed, respectively, in front of one focal point and at the back of the other focal point, and a focal point adjusting mechanism is servo-controlled in response to the outputs from the two light detectors. Each of the light detectors has a central light-receiving surface on the optical axis and a peripheral light-receiving surface in the periphery of the central light-receiving surface. According to a first method, the focal point adjusting mechanism is servo-controlled such that the deviation will become zero between the ratio of the amount of light received in the center to the total amount of light received in the center and periphery of the first light detector and the ratio of the amount of light in the center to the total amount of light in the center and periphery of the second light detector. Even if the two detectors receive different amounts of light, the difference is cancelled between the denominator and the numerator of the ratio of the amount of light in the center to the total amount of light in the center and periphery, and the device is not affected by the imbalance in the amount of light. According to a second method, the focal point adjusting mechanism is basically servo-controlled based on the difference between the amounts of light received in the centers of the two light detectors. Here, the difference in the total amount of light received by the two light detectors is calculated throughout all stages, and the difference is used to calculate a correction value multiplied by the component ratio of the amount of light in the center to the total amount of the light received in a focused condition. Since the calculated correction value is subtracted from the difference in the amount of light received in the centers, the servo output does not contain imbalance in the amount of light falling on the light detectors of the two systems, and the device is not affected by the imbalance in the amount of incident light.

    CONVERSION ADAPTOR FOR WAVE DIGITAL FILTER AND BALANCING NETWORK USING WAVE DIGITAL FILTER
    39.
    发明申请
    CONVERSION ADAPTOR FOR WAVE DIGITAL FILTER AND BALANCING NETWORK USING WAVE DIGITAL FILTER 审中-公开
    波形数字滤波器和平衡滤波器的转换适配器使用波数字滤波器

    公开(公告)号:WO1991003872A1

    公开(公告)日:1991-03-21

    申请号:PCT/JP1990001120

    申请日:1990-08-31

    Inventor: FUJITSU LIMITED

    CPC classification number: H03H17/0201

    Abstract: A balancing network of wave digital filter type consisting of three-terminal-pair conversion adaptors (21 to 26) connected in cascade each of which having a capacitor (C) and a resistor (R) as constituent elements to exhibit a filter operation function. Based on the fact that no wave is reflected by a terminal pair other than the two terminal pairs for cascade connection of the conversion adaptors (22, 24, 26) that include the resistor (R), the above terminal pair is excluded and these adaptors are combined with the neighboring conversion adaptors (21, 23, 25) that include the capacitor (C) in order to form a new three-terminal-pair-combined conversion adaptor (41) which realizes a filter function with an operation amount which is smaller than the sum of operation amounts of the three-terminal-pair conversion adaptors (21 to 26).

    DIGITAL-TO-ANALOG CONVERTER
    40.
    发明申请
    DIGITAL-TO-ANALOG CONVERTER 审中-公开
    数字到模拟转换器

    公开(公告)号:WO1991003105A1

    公开(公告)日:1991-03-07

    申请号:PCT/JP1990001055

    申请日:1990-08-20

    Inventor: FUJITSU LIMITED

    CPC classification number: H03M1/70 H03M1/808

    Abstract: A digital-to-analog converter of the current addition type using weighting resistors has an input resistance network (4) that produces a resistance corresponding to an input digital signal that consists of predetermined bits, and an adder (3) that has a first input terminal connected to the input resistance network and a second input terminal set to a reference potential to add signals on the first and second input terminals. The adder has an output terminal that outputs the result of addition which corresponds to an analog signal that is corresponded to said input digital signal. The digital-to-analog converter is placed between the first input terminal and the output terminal of the adder. This converter further includes a feedback resistance network (5) for producing a feedback resistance corresponding to a control signal indicative of the magnitude of said input digital signal, and a feedback resistance network control circuit (7) responsive to said input signal for producing said control signal indicative of the magnitude of said input digital signal.

Patent Agency Ranking