利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

260 条记录 (耗时 0.021 秒)

    DYNAMIC VOLTAGE REGULATOR SENSING AND REFERENCE VOLTAGE SETTING TECHNIQUES FOR MULTIPLE GATED LOADS
    2.
    发明申请
    DYNAMIC VOLTAGE REGULATOR SENSING AND REFERENCE VOLTAGE SETTING TECHNIQUES FOR MULTIPLE GATED LOADS 审中-公开
    多门控负载的动态电压调节器检测和参考电压设置技术

    公开(公告)号：WO2017176341A1

    公开(公告)日：2017-10-12

    申请号：PCT/US2017/012406

    申请日：2017-01-06

    申请人： INTEL CORPORATION

    发明人： JAIN, Amit, K. ,  SHEKHAR, Sameer

    IPC分类号： H02M3/155 ,  H02M1/00

    CPC分类号： G11C5/147 ,  G05F3/02 ,  G06F1/26 ,  G06F1/28

    摘要： Methods and apparatus relating to dynamic voltage regulator sensing and/or reference voltage setting techniques for multiple gated loads are described. In an embodiment, voltage regulator logic is coupled to one or more loads. Each of the one or more loads is in a separate power domain. The voltage regulator logic controls a sensed voltage from the one or more loads in response to a power gate control signal. Other embodiments are also disclosed and claimed.

    摘要翻译： 描述了涉及用于多个门控负载的动态电压调节器感测和/或基准电压设置技术的方法和设备。 在一个实施例中，电压调节器逻辑被耦合到一个或多个负载。 一个或多个负载中的每一个都位于独立的电源域中。 电压调节器逻辑响应于功率门控制信号来控制来自一个或多个负载的感测电压。 其他实施例也被公开和要求保护。

    VOLTAGE LEVEL DETECTION AND ANALOG CIRCUIT ARRANGEMENTS FOR MEMORY SYSTEMS
    3.
    发明申请
    VOLTAGE LEVEL DETECTION AND ANALOG CIRCUIT ARRANGEMENTS FOR MEMORY SYSTEMS 审中-公开
    用于存储器系统的电压电平检测和模拟电路装置

    公开(公告)号：WO2017062147A1

    公开(公告)日：2017-04-13

    申请号：PCT/US2016/051835

    申请日：2016-09-15

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： CHI, Steve, Xiaofeng ,  BHUIYAN, Ekram, Hossain

    IPC分类号： G11C16/30 ,  G11C5/14

    CPC分类号： G06F1/28 ,  G06F1/10 ,  G11C5/147 ,  G11C16/30

    摘要： An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.

    摘要翻译： 设备可以包括检测电路，其被配置为检测主机时钟线上的主机时钟信号的存在，并且在检测到主机时钟信号时检测主机电源电压的电平。 检测电路可以基于检测到的主电源电压的电平将调节器配置为调节模式或旁路模式。 此外，非易失性存储器系统的模拟电路的组件可以被划分成不同的电源电压域，其中这些组件在休眠状态期间接收一个电源电压并且那些组件在睡眠状态期间不接收不同的电源电压时是无效的。

    NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT
    6.
    发明申请
    NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT 审中-公开
    负压高压开关电路

    公开(公告)号：WO2016200446A1

    公开(公告)日：2016-12-15

    申请号：PCT/US2016/019049

    申请日：2016-02-23

    申请人： CYPRESS SEMICONDUCTOR CORPORATION

    发明人： MOSCALUK, Gary ,  GEORGESCU, Bogdan ,  WILLIAMS, Timothy

    IPC分类号： H03K17/687 ,  G11C16/02 ,  G11C16/30

    CPC分类号： H03K17/04123 ,  G11C5/147 ,  G11C5/148 ,  G11C7/1084 ,  G11C11/2297 ,  G11C11/417 ,  G11C16/30 ,  G11C17/08 ,  H03K3/356182 ,  H03K19/017 ,  H03K19/018507

    摘要： A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

    摘要翻译： 偏置电路包括包括第一晶体管和第二晶体管的级联晶体管。 第一晶体管的第一栅极在第一节点耦合到第二晶体管的第二栅极。 电路还包括耦合到第一晶体管或第二晶体管中的至少一个的电压控制电路。 电压控制电路被配置为根据输入信号的状态变化而改变第一晶体管或第二晶体管中的至少一个的电压电平，以允许输出信号的电压域转变，而不会使输入信号的电源信号 偏置电路。

    STATUS SIGNAL COMBINED ONTO POWER VOLTAGE
    7.
    发明申请
    STATUS SIGNAL COMBINED ONTO POWER VOLTAGE 审中-公开
    状态信号组合在电源上

    公开(公告)号：WO2016171680A1

    公开(公告)日：2016-10-27

    申请号：PCT/US2015/027028

    申请日：2015-04-22

    申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    发明人： BENEDICT, Melvin K.

    IPC分类号： G11C5/14 ,  G11C16/06

    CPC分类号： G11C5/14 ,  G11C5/04 ,  G11C5/147

    摘要： An electronic device includes a power pin to receive a power voltage from a power supply. A controller is to determine whether a status signal combined onto the power voltage is received through the power pin, and indicate a health of the power supply based on the determining.

    摘要翻译： 电子设备包括从电源接收电源电压的电源引脚。 控制器用于确定通过电源引脚是否接收到组合在电源电压上的状态信号，并且基于确定来指示电源的健康状况。

    SELECTIVE COUPLING OF POWER RAILS TO A MEMORY DOMAIN(S) IN A PROCESSOR-BASED SYSTEM
    8.
    发明申请
    SELECTIVE COUPLING OF POWER RAILS TO A MEMORY DOMAIN(S) IN A PROCESSOR-BASED SYSTEM 审中-公开
    电力轨道的选择性耦合到基于处理器的系统中的存储器域

    公开(公告)号：WO2016168238A1

    公开(公告)日：2016-10-20

    申请号：PCT/US2016/027197

    申请日：2016-04-13

    申请人： QUALCOMM INCORPORATED

    发明人： KOLLA, Yeshwant, Nagaraj ,  NATEKAR, Neel, Shashank

    IPC分类号： G06F1/32 ,  G11C5/14 ,  G06F1/26

    CPC分类号： G06F1/3234 ,  G06F1/263 ,  G06F1/3287 ,  G11C5/063 ,  G11C5/147 ,  Y02D10/171

    摘要： Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail, power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However, if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality, the power rail selection circuit is configured to couple the memory domain to separate memory power rail.

    摘要翻译： 公开了将电源轨与基于处理器的系统中的存储器域的选择性耦合，例如减少或避免在逻辑域中提供有意的去耦电容的需要。 为了避免或减少在逻辑域中提供额外的故意去耦电容以减轻逻辑电源轨上的电压下降，提供了电力轨道选择电路。 电源轨选择电路被配置为当逻辑电源轨可以满足存储器阵列的最小工作电压时将存储器域耦合到逻辑电源轨。 存储器阵列的附加固有解耦电容耦合到逻辑电源轨。 然而，如果当逻辑域不需要更高的操作功能时，如果逻辑电源轨的工作电压按比例缩小到存储器阵列的最小工作电压以下，则电源轨选择电路被配置为将存储器域耦合到分离的存储器电源 轨。

    APPARATUSES AND METHODS FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION IN A MEMORY
    9.
    发明申请
    APPARATUSES AND METHODS FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION IN A MEMORY 审中-公开
    用于补偿存储器中的过程，电压和温度变化的装置和方法

    公开(公告)号：WO2016077970A1

    公开(公告)日：2016-05-26

    申请号：PCT/CN2014/091329

    申请日：2014-11-17

    申请人： MICRON TECHNOLOGY, INC. ,  CHEN, Jiawei

    发明人： CHEN, Jiawei

    IPC分类号： H03H11/28

    CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/14 ,  G11C16/26 ,  G11C16/28 ,  H03K19/018521

    摘要： Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example apparatus may be a memory circuit. A pre-driver circuit and driver circuit may be associated with the memory circuit. A reference generator may provide the pre-driver circuit with reference signals that are insensitive to process, voltage, and temperature. The pre-driver circuit may receive the reference signals and the pre-driver circuit output ramping rate may then be made less sensitive to variations in process, voltage, and temperature. The pre-driver circuit output may then be supplied to a driver circuit that may then output a final driver data output with reduced noise.

    摘要翻译： 描述了用于补偿装置中过程，电压，温度或其组合上的变化的系统和方法。 示例性装置可以是存储器电路。 预驱动器电路和驱动器电路可以与存储器电路相关联。 参考发生器可以为预驱动器电路提供对过程，电压和温度不敏感的参考信号。 预驱动器电路可以接收参考信号，然后可以使预驱动器电路输出斜坡率对过程，电压和温度的变化较不敏感。 然后可以将预驱动器电路输出提供给驱动器电路，然后可以以降低的噪声输出最终的驱动器数据输出。