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    A TRANSCONDUCTANCE CURRENT SOURCE
    31.
    发明申请
    A TRANSCONDUCTANCE CURRENT SOURCE 审中-公开
    交流电流源

    公开(公告)号：WO2017046069A1

    公开(公告)日：2017-03-23

    申请号：PCT/EP2016/071529

    申请日：2016-09-13

    Applicant: FIRECOMMS LIMITED

    Inventor： MURPHY, Patrick ,  DONOVAN, Colm ,  CAHILL, Ciaran

    IPC: H03F3/345 ,  H03F3/08 ,  H03F3/50 ,  H03F1/22 ,  H03F1/32

    CPC classification number: H03F3/345 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/082 ,  H03F3/505 ,  H03F2200/456 ,  H03F2203/5031

    Abstract: A transconductance circuit has an input terminal (V IN ) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (V IN ); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit (2) provides a lower bias voltage for the second current source than for the first current source.

    Abstract translation: 跨导电路具有输入端（VIN）和输出端（Out），具有连接到所述输入端（VIN）的栅极的第一电流源（4）; 和与所述第一电流源并联的第二电流源（5），并且具有比第一电流源更高的跨导和更宽的动态范围。 电流源被配置为使得在低输入电压下，仅第一电流源（4）导通。 电压降电路（2）为第二电流源提供比第一电流源低的偏置电压。

    LOW VOLTAGE MULTI-STAGE AMPLIFIER
    32.
    发明申请
    LOW VOLTAGE MULTI-STAGE AMPLIFIER 审中-公开
    低电压多级放大器

    公开(公告)号：WO2014018935A1

    公开(公告)日：2014-01-30

    申请号：PCT/US2013/052405

    申请日：2013-07-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： DHANASEKARAN, Vijayakumar

    IPC: H03F1/02 ,  H03F3/21 ,  H03F3/30 ,  H03F3/345

    CPC classification number: H03F3/45179 ,  H03F1/0261 ,  H03F1/22 ,  H03F1/223 ,  H03F3/211 ,  H03F3/3022 ,  H03F3/345 ,  H03F2200/405 ,  H03F2200/408 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/61

    Abstract: A low voltage multi-stage amplifier (306) is described. The low voltage multi-stage amplifier (306) includes one or more prior stages (310, 312). The low voltage multi-stage amplifier (306) also includes a supply stage (314). The low voltage multi-stage amplifier (306) further includes an output stage (316) that operates with a supply voltage as low as a sum of a threshold voltage of a first transistor (347) in the output stage (316) and a saturation voltage of a second transistor (344) of the supply stage (314). The supply stage (314) supplies the output stage (316).

    Abstract translation: 描述低电压多级放大器（306）。 低电压多级放大器（306）包括一个或多个先前级（310,312）。 低电压多级放大器（306）还包括供电级（314）。 低电压多级放大器（306）还包括输出级（316），其以低于输出级（316）中的第一晶体管（347）的阈值电压和低于饱和电压 电源级（314）的第二晶体管（344）的电压。 供应级（314）供应输出级（316）。

    ARRANGEMENT FOR CALIBRATING THE QUIESCENT OPERATING POINT OF A PUSH-PULL AMPLIFIER
    33.
    发明申请
    ARRANGEMENT FOR CALIBRATING THE QUIESCENT OPERATING POINT OF A PUSH-PULL AMPLIFIER 审中-公开
    用于校准推拉放大器的等级操作点的布置

    公开(公告)号：WO2010018528A1

    公开(公告)日：2010-02-18

    申请号：PCT/IB2009/053509

    申请日：2009-08-10

    Applicant: NXP B.V. ,  BREKELMANS, Johannes Hubertus Antonius

    Inventor： BREKELMANS, Johannes Hubertus Antonius

    IPC: H03F1/30 ,  H03F1/32 ,  H03F3/30 ,  H03F3/345

    CPC classification number: H03F1/308 ,  H03F1/3217 ,  H03F3/3028 ,  H03F3/345 ,  H03F2203/30003 ,  H03F2203/30033

    Abstract: A signal processing arrangement comprises an amplifier (AMP V1 ) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, -). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1 ) and adjusts the control signal (CS) so that the even order distortion is below a critical level.

    Abstract translation: 信号处理装置包括放大器（AMP V1），其包括具有串联布置在两条电源线（+， - ）之间的相反导电类型的互补晶体管（MP3，MN3）的平台。 提供了可控偏置电路（CCS），用于根据控制信号（CS）来改变级的静态工作点。 控制装置测量放大器（AMP V1）的偶数阶失真5并调整控制信号（CS），使偶数阶失真低于临界水平。

    CURRENT SENSE FET
    34.
    发明申请
    CURRENT SENSE FET 审中-公开
    电流感应场效应管

    公开(公告)号：WO2006090333A1

    公开(公告)日：2006-08-31

    申请号：PCT/IB2006/050568

    申请日：2006-02-22

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  HEPPENSTALL, Keith ,  KENNEDY, Ian ,  FULLER, Ronald

    Inventor： HEPPENSTALL, Keith ,  KENNEDY, Ian ,  FULLER, Ronald

    IPC: H03F3/345 ,  H03F1/52 ,  H02H11/00

    CPC classification number: H03F3/345 ,  H03F1/523

    Abstract: A device includes a main field effect transistor (10) and a sense field effec transistor (12) with common drain and common gate. A controlled current source (30) supplies current to the source (22) of the sense field effect transistor. The current supply of the controlled current source (30) comes from gate terminal 4. The controlled current source (30) has differential inputs (32,34) connected to the source (20) of the main FET and the source ( 22) of the sense FET. The control current source (20) targets a zero voltage between its differential inputs and hence targets a sense current that is a fixed, small proportion of the main current through the source of the main FET (10) . This current is supplied from gate terminal 4 providing a current sense function in a three terminal ( 4,6,8) package.

    Abstract translation: 一种器件包括具有公共漏极和公共栅极的主场效应晶体管（10）和感测场效应晶体管（12）。 受控电流源（30）向感测场效应晶体管的源极（22）提供电流。 受控电流源（30）的电流源自栅极端子4.受控电流源（30）具有连接到主FET的源极（20）的差分输入（32,34）和源极（22）的源极 感测FET。 控制电流源（20）在其差分输入之间目标为零电压，因此目标是通过主FET（10）的源极的主电流的固定的小比例的感测电流。 该电流从提供三端（4,6,8）封装中的电流检测功能的栅极端子4提供。

    HIGH-FREQUENCY AMPLIFIER CIRCUIT WITH NEGATIVE IMPEDANCE CANCELLATION
    36.
    发明申请
    HIGH-FREQUENCY AMPLIFIER CIRCUIT WITH NEGATIVE IMPEDANCE CANCELLATION 审中-公开
    具有负阻抗消除功能的高频放大器电路

    公开(公告)号：WO0201709A3

    公开(公告)日：2002-07-18

    申请号：PCT/EP0106958

    申请日：2001-06-19

    Applicant: KONINKL PHILIPS ELECTRONICS NV

    Inventor： LUO SIFEN ,  SOWLATI TIRDAD

    IPC: H03F1/02 ,  H03F1/30 ,  H03F3/19 ,  H03F3/193 ,  H03F3/343 ,  H03F3/345

    CPC classification number: H03F3/19 ,  H03F1/301 ,  H03F3/193 ,  H03F3/3432 ,  H03F3/345

    Abstract: A high-frequency amplifier circuit includes an amplifying transistor and a driver transistor, with the amplifying transistor being connected in either a common emitter or a common source configuration and the driver transistor being connected in a corresponding common collector or a common drain configuration, depending upon whether bipolar or field effect transistors are used. A current-mirror bias circuit is coupled between an input terminal and an output terminal of the driver transistor, with a resistor being provided for coupling the current mirror to the input terminal of the driver transistor. The resistor, which typically has a value of between about 20 and 100 ohms, provides a negative impedance cancellation effect while minimizing power consumption at low bias levels.

    Abstract translation: 高频放大器电路包括放大晶体管和驱动晶体管，放大晶体管以公共发射极或公共源配置连接，驱动晶体管连接在相应的公共集电极或公共漏极配置中，具体取决于 是否使用双极或场效晶体管。 电流镜偏置电路耦合在驱动晶体管的输入端和输出端之间，提供电阻用于将电流镜耦合到驱动晶体管的输入端。 通常具有约20和100欧姆之间的值的电阻器提供负阻抗消除效应，同时使低偏置电平下的功率消耗最小化。

    VOLTAGE REGULATOR CIRCUIT
    37.
    发明申请
    VOLTAGE REGULATOR CIRCUIT 审中-公开
    电压调节器电路

    公开(公告)号：WO01092977A3

    公开(公告)日：2002-06-13

    申请号：PCT/US2001/014543

    申请日：2001-05-07

    IPC: G05F1/10 ,  G05F1/46 ,  G05F1/56 ,  G05F1/575 ,  H03F3/345 ,  H03F3/347

    CPC classification number: G05F1/465 ,  G05F1/575 ,  Y10S323/901

    Abstract: The performance of the main regulatory transistor of an on-chip voltage regulator circuit is enhanced when the main transistor is appropriately biased during start up. In an example embodiment, a voltage regulator circuit includes a thin gate oxide transistor as the main regulatory transistor and an operational amplifier that is referenced to a midlevel operating voltage. During start-up, the potential voltage difference is large enough to necessitate the disconnection of the main transistor from the operational amplifier. A voltage divider ladder circuit is used to maintain the gate voltage of the main transistor at the midlevel voltage while a smaller thick gate oxide transistor is used to maintain loop stability and to withstand voltage transients.

    Abstract translation: 当主晶体管在启动期间被适当地偏置时，片上稳压器电路的主调节晶体管的性能得到增强。 在一个示例性实施例中，电压调节器电路包括作为主调节晶体管的薄栅氧化物晶体管和参考中间工作电压的运算放大器。 在启动期间，电压差大到足以使主晶体管与运算放大器断开连接。 分压梯形电路用于将主晶体管的栅极电压维持在中间电压，而较小的栅极氧化物晶体管用于保持环路稳定性并承受电压瞬变。

    A HIGH FREQUENCY AMPLIFIER, AND A COMMUNICATION RECEIVER OR TRANSCEIVER
    38.
    发明申请
    A HIGH FREQUENCY AMPLIFIER, AND A COMMUNICATION RECEIVER OR TRANSCEIVER 审中-公开
    高频放大器和收发器或通信接收器

    公开(公告)号：WO99014854A2

    公开(公告)日：1999-03-25

    申请号：PCT/IB1998/001261

    申请日：1998-08-17

    IPC: H03F1/42 ,  H03F1/02 ,  H03F3/189 ,  H03F3/345 ,  H03F3/72 ,  H04B1/18 ,  H04B1/28

    CPC classification number: H03F3/72 ,  H03F3/345 ,  H04B1/28

    Abstract: Known is a two stage high frequency amplifier preceded by a large amplification gain stage providing a fixed swing signal for the two stage amplifier. Particularly in portable devices such as pagers, and mobile or cordless phones, such a receiver structure consumes much power. An amplifier structure is proposed with a cascade of at least four amplifier stages, alternately resistive feedback amplifier stages and non-resistive amplifier stages. Herewith, a dramatic improvement of the gain-bandwidth product is achieved, for the same static power consumption. The amplifier can be used in a PLL of a synthesizer circuit for a pager, cellular or cordless phone, or any other suitable communcation device.

    Abstract translation: 两级高频放大器是已知的，其前置于为所述两级放大器产生固定偏移信号的预放大级，并且消耗大量能量，尤其是在便携式设备中，例如寻呼机和 无线或手机。 本发明涉及一种具有级联至少四个放大器级的放大器结构，其交替地包括电阻反应放大器级和非电阻反应放大器级。 在所述结构中，对于相同的静态能量消耗，增益带产品得到实质性改善。 本发明的放大器可以用于寻呼机，无线或蜂窝电话或任何其他合适的通信设备的合成器电路的锁相环中。

    演算増幅器
    39.
    发明申请
    演算増幅器 审中-公开

    公开(公告)号：WO2021070246A1

    公开(公告)日：2021-04-15

    申请号：PCT/JP2019/039650

    申请日：2019-10-08

    Applicant: 三菱電機株式会社

    Inventor： 小島　友和

    IPC: H03F3/45 ,  H03F3/34 ,  H03F3/345

    Abstract: 演算増幅器（１００）は、供給された第１及び第２の電圧（ＶＤＤ，ＧＮＤ）の全電圧範囲を入出力範囲として動作する。能動負荷（３３０）は、第１導電型の電界効果トランジスタで構成される。第１及び第２の差動対（３１０，３２０）は、第２導電型の電界効果トランジスタによって構成される。第１の差動対（３１０）は、入力電圧（Ｖｉｎｐ）が第２の電圧（ＧＮＤ）のときに差動増幅が可能に構成され、第２の差動対（３２０）は、入力電圧（Ｖｉｎｐ）が第１の電圧（ＶＤＤ）のときに差動増幅が可能に構成される。第１及び第２の差動対（３１０，３２０）の少なくとも一方に対して、オフセット電圧を補正するためのオフセット補正回路（４１０，４２０）が配置される。

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