DISCRETE TIME RECEIVER
    2.
    发明申请
    DISCRETE TIME RECEIVER 审中-公开
    离职时间接收器

    公开(公告)号:WO2010078276A1

    公开(公告)日:2010-07-08

    申请号:PCT/US2009/069618

    申请日:2009-12-28

    CPC classification number: H04B1/28

    Abstract: A discrete time receiver includes a low noise transconductance amplifier (LNTA), a discrete time sampler, a passive discrete time circuit, and a switched capacitor amplifier. The LNTA amplifies a received RF signal and provides an amplified RF signal. The discrete time sampler samples the amplified RF signal (e.g., with multiple phases of a sampling clock) and provides first analog samples. The passive discrete time circuit decimates and filters the first analog samples and provides second analog samples. The switched capacitor amplifier amplifies the second analog samples and provides third analog samples. The discrete time receiver may further include a second passive discrete time circuit, a second switched capacitor amplifier, and an analog-to-digital converter (ADC) that digitizes baseband analog samples and provides digital samples. The discrete time receiver can flexibly support different system bandwidths and center frequencies.

    Abstract translation: 离散时间接收器包括低噪声跨导放大器(LNTA),离散时间采样器,无源离散时间电路和开关电容放大器。 LNTA放大接收的RF信号并提供放大的RF信号。 离散时间采样器对放大的RF信号(例如,采样时钟的多个相位)进行采样并提供第一模拟采样。 无源离散时间电路对第一个模拟采样进行抽取和滤波,并提供第二个模拟采样。 开关电容放大器放大第二模拟采样并提供第三模拟采样。 离散时间接收机可以进一步包括第二无源离散时间电路,第二开关电容放大器以及对基带模拟采样进行数字化并提供数字样本的模数转换器(ADC)。 离散时间接收器可以灵活地支持不同的系统带宽和中心频率。

    VORRICHTUNG UND VERFAHREN ZUM EMPFANGEN EINES INFORMATIONSSIGNALS MIT EINEM INFORMATIONSSIGNALSPEKTRUM
    3.
    发明申请
    VORRICHTUNG UND VERFAHREN ZUM EMPFANGEN EINES INFORMATIONSSIGNALS MIT EINEM INFORMATIONSSIGNALSPEKTRUM 审中-公开
    设备和方法,用于接收信息信号与信息信号频谱

    公开(公告)号:WO2009036981A1

    公开(公告)日:2009-03-26

    申请号:PCT/EP2008/007834

    申请日:2008-09-18

    Inventor: PERTHOLD, Rainer

    CPC classification number: H04B1/28

    Abstract: Eine Vorrichtung (10) zum Empfangen eines Informationssignals (S HF (t)) mit einem Informationssignalspektrum (S HF (f)), mit einer Mehrzahl von Empfängern (12-n) zum Erzeugen jeweils eines Einzelsignals (s n [k] ) aus dem Informationssignal, wobei jeder der Mehrzahl von Empfängern einen Mischer (31-n) zum Abwärtsmischen des Informationssignals mit einem jeweiligen Abwärtsmischsignal (32-n) aufweist, und sich die Abwärtsmischf requenzen (f LO ,n ) unterscheiden, so dass Spektren der Einzelsignale (S n (f) ) jeweils einem unterschiedlichen Teil des Informationssignalspektrums entsprechen, und einer Einrichtung (14) zum Kombinieren der Einzelsignale (s n [k]) in ein kombiniertes Signal, so dass das Spektrum (S ges (f)) des kombinierten Signals das Informationssignalspektrum (S HF (f)) nachbildet.

    Abstract translation: 用于与信息信号频谱接收信息信号(SHF(t))的一个装置(10)(SHF(F)),与用于产生每个单独的信号的多个接收器(12-n)的从信息信号(S N [K]), 其中,所述多个具有用于与相应的缩混信号(32-n),以及所述Abwärtsmischfrequenzen缩混的信息信号的混频器(31-n)的接收器中的(F LO,n)的不同,所以各个信号的那个光谱(SN(F) ),每个对应于信息信号频谱的不同部分,以及装置(用于组合各个信号(S N [K])成组合信号14),从而使光谱(STOT(F)的组合信号的((SHF F)),信息信号频谱 )复制。

    SATELLITE SIGNAL FREQUENCY TRANSLATION AND STACKING
    4.
    发明申请
    SATELLITE SIGNAL FREQUENCY TRANSLATION AND STACKING 审中-公开
    卫星信号频率的翻译和叠加

    公开(公告)号:WO2008064371A3

    公开(公告)日:2008-11-20

    申请号:PCT/US2007089192

    申请日:2007-12-31

    CPC classification number: H04H40/90 H04B1/16 H04B1/28

    Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.

    Abstract translation: 室外卫星接收单元(ODU)接收几个独立的卫星信号,用开关矩阵选择两个信号,将这两个信号下变频为具有高频和低频信号的频带叠加信号,并将同一电缆上的频带叠加信号输出到接收机 单位。 多个卫星信号可以分两组或多组选择并输出到独立的接收机单元。 在接收的射频(RF)处执行信号选择,并且通过单个下变频步骤执行频带堆叠至中频(IF)。 在IF输出端组合之前,通过使用频率捷变下变频器和带通滤波器,可以在多个卫星的两个以上信道的相同电缆上进行信道堆叠。 慢速转换开关在开关时将信号干扰降至最低,并将输入阻抗保持在恒定值。

    TRANSCEIVERS
    5.
    发明申请
    TRANSCEIVERS 审中-公开
    收发器

    公开(公告)号:WO2008017805A3

    公开(公告)日:2008-06-19

    申请号:PCT/GB2007002683

    申请日:2007-07-16

    Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency that is higher than the reception.

    Abstract translation: RF收发器装置包括发射机电路,其被布置为将信号从基带频率转换成RF传输频率,并且接收器电路被布置成将信号从RF接收频率转换为基带频率。 发射机和接收机电路各自包括三个混频器,其被布置成在基带频率,第一中频之间转换信号; 高于传输频率的第二中频; 和高于接收的第二中频。

    PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS
    6.
    发明申请
    PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS 审中-公开
    包装天线与集成电路

    公开(公告)号:WO2006133108A3

    公开(公告)日:2007-11-29

    申请号:PCT/US2006021770

    申请日:2006-06-05

    Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips and antenna devices which are integrally constructed from package frame structures (e.g., lead frame, package carrier, package core, etc.), to thereby form compact integrated radio/wireless communications systems for millimeter wave applications. For example, an electronic apparatus (30) includes a package frame (11) having an antenna (12) that is integrally formed as part of the package frame (11), an IC (integrated circuit) chip (13) mounted to the package frame (11), interconnects (19) that provide electrical connections to the IC chip (13) and the antenna (12), and a package cover (15).

    Abstract translation: 提供了用于整体封装由封装框架结构(例如,引线框架,封装载体,封装芯等)整体构建的半导体IC(集成电路)芯片和天线装置的集成封装,从而形成紧凑的集成无线电/无线 通信系统用于毫米波应用。 例如,电子设备(30)包括具有整体形成为封装框架(11)的一部分的天线(12)的封装框架(11),安装在封装框架(11)上的IC(集成电路)芯片 框架(11),提供到IC芯片(13)和天线(12)的电连接的互连(19)和封装盖(15)。

    RF-TO-BASEBAND RECEIVER ARCHITECTURE
    7.
    发明申请
    RF-TO-BASEBAND RECEIVER ARCHITECTURE 审中-公开
    射频基带接收机架构

    公开(公告)号:WO2007104131A1

    公开(公告)日:2007-09-20

    申请号:PCT/CA2007/000276

    申请日:2007-02-22

    CPC classification number: H04B1/28

    Abstract: An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LO 105 is thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filter 110 and complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL). For example, transceiver channels may be designed on the basis that the RF frequency F R1 is assigned a value of (n±¼)•f s , where the frequency f PLL of the PLL may be chosen to be twice the sub-sampling frequency f s and the frequency f Rx LO of the Rx LO may be nine times the frequency f PLL .

    Abstract translation: 提供了一种用于无线收发器(例如,用于耳机)的改进的接收器架构和方法,由此接收器有利地仅使用一个合成器电路用于RF至IF和IF至基带频带转换过程,其中 反过来又提供较低的功耗。 接收机包括用于第一混频级(即RF至IF转换)的注入锁定本地接收机振荡器(Rx LO)。 因此,Rx LO 105能够使用由该合成器(例如,分数N锁相环电路(PLL))产生的相对低的参考频率信号的高电平谐波。 接收机还包括可调Q增强IF滤波器110和用于第二转换级(即IF到基带转换)的复数次采样和混合下转换电路。 用于第二转换级的采样频率是从合成器(PLL)导出的参考频率的谐波。 例如,可以基于RF频率F SUB R1分配值(n±¼)f S s S s来设计收发器信道,其中频率f PLL的PLL 可以选择为子采样频率f SUB的两倍,并且Rx LO的频率f RxLO 可以是9倍 频率f PLL PLL。

    DISPOSITIF DE RECEPION ET/OU D'EMISSION DE SIGNAUX RADIOFREQUENCES A REDUCTION DU BRUIT
    8.
    发明申请
    DISPOSITIF DE RECEPION ET/OU D'EMISSION DE SIGNAUX RADIOFREQUENCES A REDUCTION DU BRUIT 审中-公开
    用于接收和/或发送具有噪声减少的无线电频率信号的设备

    公开(公告)号:WO2007101885A1

    公开(公告)日:2007-09-13

    申请号:PCT/EP2007/052241

    申请日:2007-03-09

    CPC classification number: H04B1/28

    Abstract: Le dispositif de réception et/ou d'émission de signaux radiofréquences comprend une antenne (8) pour capter ou transmettre des signaux radiofréquences, un filtre passe-bande (9), au moins un amplificateur à faible bruit (11) pour amplifier les signaux filtrés, un étage oscillateur (1) pour générer des premiers signaux haute fréquence (SVCO), au moins un diviseur de fréquence (14) pour diviser par M la fréquence des premiers signaux afin de générer des seconds signaux haute fréquence (SD), où M est un nombre entier plus grand que 1, au moins un premier bloc mélangeur (12) pour mélanger les signaux radiofréquences filtrés et amplifiés (SR) avec les premiers signaux haute fréquence (SVCO), et au moins un second bloc mélangeur (13) pour mélanger les signaux intermédiaires fournis par le premier bloc mélangeur avec les seconds signaux haute fréquence afin de produire des signaux en bande de base (IR, QR). L'étage oscillateur (1) est configuré de telle manière à générer des premiers signaux haute fréquence (SVCO), dont la fréquence est en dehors de la bande de fréquence du filtre passe-bande et plus grande d'un facteur M/N compris entre 1 et 2 que la fréquence des signaux radiofréquences reçus, où N est un nombre entier plus grand que 1.

    Abstract translation: 本发明涉及一种用于接收和/或发送射频信号的装置,包括用于捕获或发射射频信号的天线(8),带通滤波器(9),至少一个低噪声放大器(11),用于放大经滤波的信号 ,用于产生第一高频信号(SVCO)的振荡器级(1),至少一个分离器(14),用于将M个第一高频信号的频率分为第二高频信号(SD),其中M是整数 大于1,用于将滤波和放大的射频信号(SR)与第一高频信号(SVCO)混合的至少一个第一混频器模块(12)以及至少一个第二混频器模块(13),用于混合中间信号 由第一混频器块(13)传送第二高频信号以产生基带信号(IR,QR)。 振荡器级(1)被配置为产生第一高频信号(SVCO),其频率在带通滤波器的频带之外,并且在1和2之间的因子M / N的频率高于频带的频率 接收的射频信号,其中N是大于1的整数。

    DIRECT CONVERSION RECEIVER HAVING A SUBHARMONIC MIXER
    9.
    发明申请
    DIRECT CONVERSION RECEIVER HAVING A SUBHARMONIC MIXER 审中-公开
    直接转换接收器有一个亚音响混音器

    公开(公告)号:WO2007038482A2

    公开(公告)日:2007-04-05

    申请号:PCT/US2006/037420

    申请日:2006-09-26

    CPC classification number: H04B1/30

    Abstract: A differential radio frequency (RF) receiver includes a fully differential direct conversion receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a differential radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired receive LO signals.

    Abstract translation: 差分射频(RF)接收机包括完全差分直接转换接收链,接收链中的次谐波混频器,被配置为接收差分射频(RF)输入信号和本地振荡器(LO))信号的次谐波混频器, 相位移45度的合成器和具有压控振荡器并具有至少一个分频器以产生所需接收LO信号的合成器。

    CLOCKING SYSTEM USING VARIABLE CLOCK SIGNAL
    10.
    发明申请
    CLOCKING SYSTEM USING VARIABLE CLOCK SIGNAL 审中-公开
    使用可变时钟信号的时钟系统

    公开(公告)号:WO2006123264A1

    公开(公告)日:2006-11-23

    申请号:PCT/IB2006/051372

    申请日:2006-05-02

    CPC classification number: H04B1/28

    Abstract: The present invention relates to a clocking apparatus (10) and method for generating clock signals based on a variable frequency signal generated by a signal generating means (20) and controlled by a frequency control information such as a frequency control word (FCW). This information also enables to obtain, through storage means (60) storing for example a plurality of look-up tables, a processing control information provided to a digital signal processing means (50) which comprises elements sensitive to sampling frequency rate variations such as a phase shifter means (510), a filter means (520) with a configurable impulse response, and dependent on sampling frequency rate variations such as a re-sampler means (530). The variable frequency signal is used to clock an analog-to-digital converter or, as an alternative, a digital-to-analog converter at a respective sampling frequency. This sampling frequency is used by a clock generator means (30) to serve as a reference for all other clocking in the digital signal processing means (50). The re-sampler means (530) will be preferably located behind the filter means (520) and will comprise a digital oscillator (531) and a re-sampler (532) clocked by a clock signal based on said variable frequency signal and having its outgoing register clocked by a frequency generated by said digital oscillator (531).

    Abstract translation: 本发明涉及一种基于由信号发生装置(20)产生并由诸如频率控制字(FCW)等频率控制信息控制的可变频率信号产生时钟信号的计时装置(10)和方法。 该信息还能够通过存储例如多个查找表的存储装置(60)获得提供给数字信号处理装置(50)的处理控制信息,数字信号处理装置(50)包括对采样频率变化敏感的元件,例如 移相器装置(510),具有可配置的脉冲响应的滤波器装置(520),并且取决于诸如重新采样器装置(530)的采样频率变化。 可变频率信号用于以相应的采样频率对模数转换器或作为替代的数模转换器进行时钟。 该采样频率由时钟发生器装置(30)用作数字信号处理装置(50)中所有其它时钟的参考。 重采样器装置(530)将优选地位于滤波器装置(520)的后面,并且将包括数字振荡器(531)和重新采样器(532),其基于所述可变频率信号由时钟信号定时并且具有其 由所述数字振荡器(531)产生的频率计时的输出寄存器。

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