公开(公告)号：WO02067120B1

公开(公告)日：2003-04-03

申请号：PCT/US0149499

申请日：2001-12-28

Applicant: ROAD RUNNER

Inventor： GOULD KENNETH ,  SUN MICHAEL ,  CHUNG JOO YOUNG ,  HUANG FRANK

IPC: G06F11/16 ,  G06F11/20 ,  H04L12/18 ,  H04L29/06 ,  H04N21/218 ,  H04N21/6405 ,  H04N21/647 ,  G06F11/00 ,  G06F12/00 ,  G06F13/00 ,  G06F15/16 ,  H04N7/16 ,  H04N7/173

CPC classification number: H04L65/4076 ,  G06F11/16 ,  G06F11/1654 ,  G06F11/2038 ,  H04L12/1868 ,  H04L29/06027 ,  H04L29/1233 ,  H04L41/0659 ,  H04L45/28 ,  H04L61/25 ,  H04L67/1002 ,  H04L67/1023 ,  H04L69/161 ,  H04L69/22 ,  H04L69/40 ,  H04N21/2181 ,  H04N21/6405 ,  H04N21/6473

Abstract: A system and method for avoiding a single point of failure in the broadcast of streaming data. The system uses multiple redundant servers (10, 12) streaming the exactly same data to a failover device (16). The failover device buffers (20P, 20S) the streams into a primary and secondary data stream and automatically switches from the primary to the secondary data stream if it detects a corruption in the primary data stream. Since the buffered data packets of the two streams are identical and are synchronized, there is not outage for multicast receivers when the primary data source fails since there is a switch to exactly the same data in the next packet of the secondary data stream.

Abstract translation: 一种用于避免广播流数据的单点故障的系统和方法。 系统使用多个冗余服务器（10,12）将完全相同的数据流传输到故障切换设备（16）。 故障切换设备将流（20P，20S）缓冲（20P，20S）到主数据流和次数据流中，并且如果它检测到主数据流中的损坏，则自动从主数据流切换到副数据流。 由于两个流的缓冲数据包相同并且同步，当主数据源发生故障时，多播接收器不会中断，因为在次要数据流的下一个数据包中切换到完全相同的数据。

公开(公告)号：WO9930235A3

公开(公告)日：1999-08-26

申请号：PCT/SE9802267

申请日：1998-12-09

Applicant: ERICSSON TELEFON AB L M

Inventor： ROSENDAHL MICHAEL ,  JONSSON TOMAS LARS ,  HOLMBERG PER ANDERS

IPC: G06F11/10 ,  G06F11/16 ,  G06F11/18 ,  G06F11/14

CPC classification number: G06F11/1654 ,  G06F11/1641 ,  G06F11/165

Abstract: The present invention relates to a method of utilizing information made available in a bit error check of data words belonging to instructions read into a processor having a first (11) and a second (11') calculating unit which operate in parallel with one another, a so-called double processor mode. The processor structure also comprises a third and a fourth calculating unit (13, 13') intended for continuously checking for possible bit errors in read-in data words, a comparator (14) for comparing output data from parallel operating units (11, 11'), a diagnostic unit (15) adapted to determine which of the calculating units delivered correct output data when detecting a difference in output data in the comparator (14), and a control unit (16) adapted to control that the output data from the processor structure (1) originates from a calculating unit that has delivered correct output data. The processor switches to a single processor mode when a difference in output data is detected in the comparator. The data words are read directly into respective calculating units (11, 11') without correction for possible bit errors when the processor operates in a double processor mode, and the information from the third and fourth calculating units (13, 13') is used to effect said determination in the diagnostic unit (15). Bit error control and bit error correction are used in a known manner when the processor operates in a single processor mode.

Abstract translation: 本发明涉及利用在具有读取到具有彼此并行操作的第一（11）和第二（11'）计算单元的处理器中的指令的数据字的位错误校验中获得的信息的方法， 一种所谓的双处理器模式。 处理器结构还包括用于连续检查读入数据字中可能的比特错误的第三和第四计算单元（13,13'），比较器（14），用于比较来自并行操作单元（11,11）的输出数据 '），诊断单元（15），其适于在检测到所述比较器（14）中的输出数据的差异时确定传送出的正确输出数据中的哪个计算单元;以及控制单元（16），其适于控制所述输出数据 处理器结构（1）源自已传送正确输出数据的计算单元。 当在比较器中检测到输出数据的差异时，处理器切换到单处理器模式。 当处理器以双处理器模式操作时，将数据字直接读取到相应的计算单元（11,11'）中，而不对可能的位错误进行校正，并且使用来自第三和第四计算单元（13,13'）的信息 以在所述诊断单元（15）中进行所述确定。 当处理器以单个处理器模式运行时，位错误控制和位错误校正以已知的方式使用。

公开(公告)号：WO1994002896A1

公开(公告)日：1994-02-03

申请号：PCT/GB1993001514

申请日：1993-07-19

Applicant: INTEGRATED MICRO PRODUCTS LIMITED

Inventor： INTEGRATED MICRO PRODUCTS LIMITED ,  WILLIAMS, Emrys, John ,  LIDDELL, David, Charles

IPC: G06F11/00

CPC classification number: G06F11/1654 ,  G06F11/0709 ,  G06F11/079 ,  G06F11/10 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/185 ,  G06F11/20

Abstract: A fault-tolerant computer system comprises a main data bus (10) having a plurality of interface slots (18) for interconnecting a plurality of computer sub-systems (12, 14, 16...), one of which is a central processor sub-system (12) having three processor modules (20, 22, 24) operating in parallel in a substantially synchronised manner. One of the processor modules acts as master reading data from and writing data to the main data bus (10): each processor module compares data on the main data bus with data on a local bus of the module to determine any inconsistency indicating a hardware fault, and generates outputs reflecting the probability that a particular module is the source of the fault, which outputs are transmitted to the other modules over a synchronisation bus (26).

Abstract translation: 容错计算机系统包括具有多个接口槽（18）的主数据总线（10），用于互连多个计算机子系统（12,14,16 ...），其中一个是中央处理器 子系统（12）具有以基本上同步的方式并行操作的三个处理器模块（20,22,24）。 其中一个处理器模块用作从主数据总线（10）读取数据并将数据写入数据总线（10）：每个处理器模块将主数据总线上的数据与模块的本地总线上的数据进行比较，以确定指示硬件故障的任何不一致 并且产生反映特定模块是故障源的概率的输出，所述输出通过同步总线（26）发送到其他模块。