公开(公告)号：WO00034854A3

公开(公告)日：2000-10-19

申请号：PCT/EP1999/009184

申请日：1999-11-24

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/45 ,  G06F9/455

CPC classification number: G06F9/45504 ,  G06F9/3885

Abstract: A threaded interpreter (916) is suitable for executing a program comprising a series of program instructions stored in a memory (904). For the execution of a program instruction the threaded interpreter includes: a preparatory unit (918) for executing a plurality of preparatory steps making the program instruction available in the threaded interpreter, and an execution unit (920) with one or more machine instructions emulating the program instruction. According to the invention, the threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions, machine instructions implementing a first one of the preparatory steps are executed in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

Abstract translation: 多块解释器（916）可以执行包括存储在存储器（904）中的一系列程序指令的程序。 要执行的程序指令，所述多嵌段解释器包括用于执行多个预备步骤，使在多嵌段指令解释器中可用的节目的预备单元（918），和一个单元 由至少一个模拟程序指令的机器指令组成的执行（920）。 根据本发明，多嵌段外壳被构造为使得，在指令并行处理器执行一系列指令中的程序时，计算机指令执行的第一预备步骤被并行执行的与 机器指令为各个程序指令序列执行第二预备步骤。

公开(公告)号：WO00058828A1

公开(公告)日：2000-10-05

申请号：PCT/US2000/007656

申请日：2000-03-23

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/318 ,  G06F9/32 ,  G06F9/34 ,  G06F9/35 ,  G06F12/00

CPC classification number: G06F9/30192 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/325

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 从而提高性能并减少程序内存的使用。

公开(公告)号：WO0034854A2

公开(公告)日：2000-06-15

申请号：PCT/EP9909184

申请日：1999-11-24

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： HOOGERBRUGGE JAN ,  AUGUSTEIJN ALEXANDER

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/45 ,  G06F9/455 ,  G06F9/00

CPC classification number: G06F9/45504 ,  G06F9/3885

Abstract: A threaded interpreter (916) is suitable for executing a program comprising a series of program instructions stored in a memory (904). For the execution of a program instruction the threaded interpreter includes: a preparatory unit (918) for executing a plurality of preparatory steps making the program instruction available in the threaded interpreter, and an execution unit (920) with one or more machine instructions emulating the program instruction. According to the invention, the threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions, machine instructions implementing a first one of the preparatory steps are executed in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

Abstract translation: 线程解释器（916）适用于执行包括存储在存储器（904）中的一系列程序指令的程序。 为了执行程序指令，所述螺纹解释器包括：准备单元（918），用于执行使所述程序指令在所述螺纹解释器中可用的多个准备步骤，以及执行单元（920），其具有模拟所述程序指令的一个或多个机器指令 程序指令。 根据本发明，螺纹解释器被设计成使得在执行一系列程序指令的指令级并行处理器时，执行准备步骤中的第一个的机器指令与执行第二个执行步骤的机器指令并行执行 的一系列程序指令的准备步骤。

公开(公告)号：WO00022516A1

公开(公告)日：2000-04-20

申请号：PCT/US1999/023774

申请日：1999-10-11

IPC: G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3844 ,  G06F9/3846

Abstract: A branch operation is processed using a branch predict instruction (300) and an associated branch instruction. The branch predict instruction (300) indicates a predicted direction (310), a target address (320), and an instruction address (330) for the associated branch instruction. When the branch predict instruction (300) is detected, the target address (330) is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address (330). The branch predict instruction (300) may also include hint information (340) for managing the storage and use of the branch prediction information.

Abstract translation: 使用分支预测指令（300）和相关联的分支指令来处理分支操作。 分支预测指令（300）指示相关联的分支指令的预测方向（310），目标地址（320）和指令地址（330）。 当检测到分支预测指令（300）时，目标地址（330）被存储在由相关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址（330）。 分支预测指令（300）还可以包括用于管理分支预测信息的存储和使用的提示信息（340）。

公开(公告)号：WO00004444A1

公开(公告)日：2000-01-27

申请号：PCT/US1999/001047

申请日：1999-01-18

IPC: G06F9/30 ,  G06F9/315 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30069 ,  G06F9/30152 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/383 ,  G06F9/384

Abstract: An apparatus for accelerating move operations includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move instruction, the lookahead unit signals a register rename unit, which reassigns the rename register associated with the source register to the destination register. In one particular embodiment, the lookahead unit attempts to accelerate moves from a base pointer register to a stack pointer register (and vice versa). An embodiment of the lookahead unit generates lookahead values for the stack pointer register by maintaining cumulative effects of the increments and decrements of previously dispatched instructions. The cumulative effects of the increments and decrements prior to a particular instruction may be added to a previously generated value of the stack pointer register to generate a lookahead value for that particular instruction. For such an embodiment, reassigning the rename register as described above may thereby provide a valid value for the stack pointer register, and hence may allow for the generation of lookahead stack pointer values for instruction subsequent to the move instruction to proceed prior to execution of the move instruction. The present embodiment of the register rename unit may also assign the destination rename register selected for the move instruction to the source register of the move instruction (i.e. the rename tags for the source and destination are "swapped").

Abstract translation: 用于加速移动操作的装置包括在执行移动指令之前（例如，在选择用于在处理器内进行调度的移动操作）之前检测移动指令的前视单元。 在检测到移动指令时，先行单元发送寄存器重命名单元，该单元将与源寄存器相关联的重命名寄存器重新分配给目的地寄存器。 在一个特定实施例中，前瞻单元尝试加速从基本指针寄存器到堆栈指针寄存器的移动（反之亦然）。 前瞻单元的实施例通过维持先前分派的指令的增量和减量的累积效应来生成堆栈指针寄存器的前置值。 在特定指令之前的增量和减量的累积效应可以被添加到堆栈指针寄存器的先前产生的值以产生该特定指令的前瞻值。 对于这样的实施例，如上所述重新分配重命名寄存器可以由此为堆栈指针寄存器提供有效值，因此可以允许生成用于在执行移动指令之前的移动指令之后的指令的前瞻堆栈指针值 移动指令。 寄存器重命名单元的本实施例还可以将为移动指令选择的目的地重命名寄存器分配给移动指令的源寄存器（即，源和目的地的重命名标签被“交换”）。

公开(公告)号：WO00001159A1

公开(公告)日：2000-01-06

申请号：PCT/JP1999/003359

申请日：1999-06-24

IPC: G06F7/48 ,  G06F9/32 ,  H03M7/30 ,  H04N7/26 ,  H04N7/50

CPC classification number: G06F9/30094 ,  G06F7/48 ,  G06F7/49994 ,  G06F2207/3828 ,  H04N19/61

Abstract: Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incoroporating a simple circuit of the present invention into a central processing unit (CPU). The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incoporated into a processor. By incorporating a single sign(x) circuit into a processor a SISD sign(x) function can be supported. By duplicating the basic sign(x) hardware within a processor, in accordance with the present invention, a SIMD sign(x) function can be implemented.

Abstract translation: 描述了用于实现和使用sign（x）功能的方法和装置。 根据本发明，例如通过将本发明的简单电路转化为中央处理单元（CPU），以硬件实现sign（x）功能。 根据本发明实现符号（x）功能所需的硬件相对简单，并允许在单个处理器时钟周期中确定符号（x）功能。 在用于执行符号（x）功能的硬件被插入处理器的实施例中，支持处理器符号（x）命令。 通过将单符号（x）电路并入处理器，可以支持SISD符号（x）功能。 通过在处理器内复制基本符号（x）硬件，根据本发明，可以实现SIMD符号（x）功能。

公开(公告)号：WO00000878A2

公开(公告)日：2000-01-06

申请号：PCT/US1999/014299

申请日：1999-06-26

IPC: G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F

CPC classification number: G06F8/445 ,  G06F9/30072 ,  G06F9/30174 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

Abstract: A micro-architectural method increases the performance of microprocessor and digital circuit designs by increasing the usable instruction-level parallelism during execution. The method can be applied to substantially increase the performance of processors in a broad range of instruction sets including CISC, RISC, and EPIC designs. Code blocks of instructions are transformed from the original instruction set architecture to a new instruction set architecture by an instruction stream transformation unit (102). The transformed code blocks are then cached in an instruction cache (104). The process increases processor performance by substantially increasing the instruction-level parallelism available during execution by an execution unit (100).

Abstract translation: 我们的微架构过程通过增加可在执行期间使用的指令之间的并行性来提高微处理器和数字电路的性能。 该方法可用于大幅提高各种指令集体系结构（包括CISC，RISC和EPIC体系结构）中处理器的性能。 指令编码块由指令字符串变换单元变换，将指令编码块从原来的指令集架构变更为新的指令集架构。 转换后的编码块然后在指令流高速缓冲存储器中进行缓存类型管理。 这种转换方法提高了处理器的性能，因为它大大增加了执行期间可用的指令之间的并行性。

公开(公告)号：WO99060460A2

公开(公告)日：1999-11-25

申请号：PCT/US1999/011280

申请日：1999-05-21

IPC: G06F9/32 ,  G06T1/20 ,  G06F

CPC classification number: G06T1/20

Abstract: A controller for a digital processor includes a random access memory, e.g., an instruction memory, that consumes significant power when operating. To reduce the power consumption when repetitive instructions, i.e. loops, are being performed, the loop instructions are stored in and accessed from a shift register rather than from the random access memory without any special instructions defining the loop. A memory control includes a state tracking machine that monitors the execution of the program instructions and determines therefrom when a loop has been entered, whereupon it enables the shift register to produce the loop instructions stored therein and disables the instruction memory from producing instructions until the loop is exited. The foregoing process is automatically initiated for each loop, whether the loop is a new loop, a loop within a loop or a multiple loop. The present controller does not require special instructions either preceding or following a loop to specify the start or end points of the loop, or the number of instructions in the loop, or the number of times the loop is to be performed; but rather it determines the presence of a loop automatically from the executable micro-code instructions that execute the loop.

Abstract translation: 用于数字处理器的控制器包括随机存取存储器，例如在操作时消耗大量功率的指令存储器。 为了在重复指令（即循环）正在执行时降低功耗，循环指令被存储在移位寄存器中而不是来自随机存取存储器中，而不用定义循环的任何特殊指令。 存储器控制包括状态跟踪机器，其监视程序指令的执行，并且在进行循环时由其确定，从而使得移位寄存器能够产生其中存储的循环指令，并禁止指令存储器产生指令直到循环 退出了 无论循环是新循环还是循环中的循环或多循环，上述过程都将自动启动。 本控制器不需要在循环之前或之后的特定指令来指定循环的开始或结束点，或循环中的指令数量或循环执行的次数; 而是从执行循环的可执行的微代码指令中自动确定循环的存在。

公开(公告)号：WO99047999A1

公开(公告)日：1999-09-23

申请号：PCT/US1999/004887

申请日：1999-03-04

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F15/78

CPC classification number: G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

Abstract translation: 用于数字信号处理的电路要求使用可变长度指令集。 示例性DSP包括一组三个数据总线（108,110,112），数据可以通过该组数据总线与寄存器组（120）和三个数据存储器（102,103,104）交换。 可以使用具有可由至少两个处理单元（128,130）访问的寄存器的寄存器组（120）。 可以包括接收存储在指令存储器（152）中的可变长度指令的指令提取单元（156）。 指令存储器（152）可以与三组数据存储器（102,103,104）分离。

公开(公告)号：WO9928817A3

公开(公告)日：1999-07-22

申请号：PCT/SE9802205

申请日：1998-12-02

Applicant: ERICSSON TELEFON AB L M ,  ROOS TOBIAS ,  HALVARSSON DAN ,  JONSSON TOMAS

Inventor： ROOS TOBIAS ,  HALVARSSON DAN ,  JONSSON TOMAS

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F11/30 ,  G06F11/34 ,  G06F9/32

CPC classification number: G06F9/30181 ,  G06F9/261 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/30196 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3466

Abstract: In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of the computer, such as a trace enabling signal (63), influencing the translation process in the instruction decoding unit. These state signals (63) are added to the operation code (65) of the program instruction to be decoded, the operation code of the program instruction thus being extended and used as input to a translating table (55), the extended operation code of the program instruction being taken as an address of a field in the table. The addresses and thus the contents of the fields addressed for the same operation code of a program instruction can then be different for different values of the state signals. Thus generally, the state signals cause the instruction decoder to change its translating algorithm so that the decoder can decode an operation code differently depending on the state which the signals adopt. The dynamic decoding can for a trace enabling signal be used for switching on and off a trace function. In the normal case, when tracing is not desired, no microinstructions supporting the trace function have to be executed and thereby the performance and in particular the speed of the computer system will be increased.

Abstract translation: 在计算机系统中，用于将程序指令转换为微代码指令的指令解码单元动态地进行操作。 因此，单元接收指示影响指令解码单元中的转换处理的计算机的状态的状态信号，例如跟踪使能信号（63）。 这些状态信号（63）被添加到要解码的程序指令的操作代码（65）中，因此程序指令的操作代码被扩展并用作转换表（55）的输入，扩展操作代码 程序指令被视为表中字段的地址。 因此，对于不同的状态信号值，对于程序指令的相同操作代码寻址的字段的地址和因此的内容可以是不同的。 因此，通常情况下，状态信号使指令译码器改变其翻译算法，使得解码器可根据信号采用的状态对不同的操作码进行解码。 动态解码可以用于跟踪启用信号用于打开和关闭跟踪功能。 在正常情况下，当不需要跟踪时，不需要执行支持跟踪功能的微指令，从而提高计算机系统的性能，特别是速度。