公开(公告)号：WO2011092210A1

公开(公告)日：2011-08-04

申请号：PCT/EP2011/051077

申请日：2011-01-26

申请人： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS) ,  ECOLE NORMALE SUPERIEURE DE CACHAN ,  PLACKO, Dominique ,  JOUBERT, Pierre-Yves ,  BORE, thierry

发明人： PLACKO, Dominique ,  JOUBERT, Pierre-Yves ,  BORE, thierry

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/08

摘要： The invention relates to a method for modelling the interactions of a wave, generated by a source emitting an impulsive signal of arbitrary shape, with a medium, including steps involving: a) elaboration of a generic model by the method called "DPSM"; b) Fourier series decomposition of the impulsive signal c) For each of the harmonics arising from the foregoing decomposition, calculation of a model specifically for the harmonic in question from the generic model previously elaborated; and d) superposition of a set of specific models thus calculated in order to assemble a final model.

摘要翻译： 本发明涉及一种用于建模由发出任意形状的脉冲信号的源产生的波与介质的相互作用的方法，包括以下步骤：a）通过称为“DPSM”的方法阐述通用模型; b）脉冲信号的傅立叶级数分解c）对于从上述分解产生的每个谐波，从以前详细阐述的一般模型中，对所讨论谐波的模型进行计算; 以及d）由此计算的一组特定模型的叠加以便组装最终模型。

公开(公告)号：WO2010052663A3

公开(公告)日：2011-05-05

申请号：PCT/IB2009054918

申请日：2009-11-05

申请人： NXP BV ,  ONETE CRISTIAN NICOLAE

发明人： ONETE CRISTIAN NICOLAE

IPC分类号： G06N3/12

CPC分类号： G06N3/126 ,  G06F2217/08

摘要： The invention relates to an electrical circuit arrangement comprising a plurality of reconfigurable circuit cells, each reconfigurable circuit cell comprising -a plurality of nodes, -a plurality of links connectable to the nodes, -at least one circuit element, wherein the reconfigurable circuit cells are each configured to form either a node or a link of the electrical circuit arrangement. Furthermore the invention relates to a method for designing an electrical circuit arrangement

摘要翻译： 本发明涉及一种包括多个可重构电路单元的电路装置，每个可重构电路单元包括多个节点，多个可连接到节点的链路，至少一个电路元件，其中可重构电路单元是 每个被配置为形成电路装置的节点或链路。 此外，本发明涉及一种用于设计电路装置的方法

公开(公告)号：WO2010056902A2

公开(公告)日：2010-05-20

申请号：PCT/US2009064257

申请日：2009-11-12

申请人： SYNOPSYS INC ,  ISPIR MUSTAFA

发明人： ISPIR MUSTAFA

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/08

摘要： Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit operation level before using optimizing with data flow algorithm and mapping the design onto hardware. In an aspect, the present invention discloses circuit operation level optimization for data flow graph representations with optimizing zero inputs caused by the upsamplers, or with optimizing unused outputs caused by the downsamplers. In at least one embodiment of the present invention, multirate data graph is converted to a single rate data graph before data flow optimizing. In an aspect, converting a multirate data graph to a single rate data graph comprises unfolding the multirate data graph with minimum unfolding factors that are inversely proportional to the clock values.

摘要翻译： 使用展开来优化电路表示的方法和装置作为多速率折叠的预处理。 在本发明的至少一个实施例中，在使用数据流算法优化并将设计映射到硬件之前，使用电路操作级来优化电路的数据流图表示的一部分。 在一方面，本发明公开了利用由上采样器引起的优化零输入的数据流图表示，或者优化由下采样器引起的未使用输出的电路操作级优化。 在本发明的至少一个实施例中，在数据流优化之前，将多速率数据图转换为单速率数据图。 在一方面，将多速率数据图转换为单速率数据图包括以与时钟值成反比的最小展开因子展开多速率数据图。

公开(公告)号：WO2010014445A2

公开(公告)日：2010-02-04

申请号：PCT/US2009/051083

申请日：2009-07-17

申请人： SYNOPSYS, INC. ,  SINHA, Subarnarekha ,  CHIANG, Charles, C.

发明人： SINHA, Subarnarekha ,  CHIANG, Charles, C.

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/504 ,  G06F2217/08

摘要： One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value.

摘要翻译： 本发明的一个实施例提供了一种用于促进三维集成电路（3D IC）的布局规划的系统。 在操作期间，系统接收多个电路块。 系统将块放置在至少一层多层管芯结构中，并设置时变参数的初始值。 然后，系统迭代地扰乱块布置，直到时变参数达到预定值。

公开(公告)号：WO2009158466A1

公开(公告)日：2009-12-30

申请号：PCT/US2009/048607

申请日：2009-06-25

申请人： SIEMENS PRODUCT LIFECYCLE MANAGEMENT SOFTWARE INC. ,  MILLER, Justin, H.

发明人： MILLER, Justin, H.

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/509 ,  G06F2217/08 ,  G06F2217/34

摘要： A system, method, and computer program product for automated creation of collision-free paths for pipes and tubes in a CAD system. A method includes receiving inputs, in a data processing system, defining at least a start point and destination point for a pipe in a CAD environment, and a diameter for the pipe. The method includes determining sample points between the start point and destination point. The method also includes building a graph including the sample points and the start point and the destination points as nodes and a plurality of edges connecting the nodes. The method also includes computing a path through the graph between the start point and the destination point. The method also includes, for each node in the path, testing each edge connected to the node to determine if there is a collision along the edge between a test object model and a background model geometry in the CAD environment, and removing from the graph any edge that has a collision. If there is no collision along an edge of the path, then designating the path as a successful path and displaying the successful path to a user by the data processing system.

摘要翻译： 一种用于在CAD系统中自动创建管道和管道的无碰撞路径的系统，方法和计算机程序产品。 一种方法包括在数据处理系统中接收在CAD环境中至少定义管道的起始点和目的地点的输入以及管道的直径。 该方法包括确定起始点和目标点之间的采样点。 该方法还包括构建包括采样点和起始点和目的地点作为节点的图形以及连接节点的多个边缘。 该方法还包括计算通过起始点和目的地点之间的图形的路径。 该方法还包括，对于路径中的每个节点，测试连接到节点的每个边缘，以确定沿着CAD环境中的测试对象模型和背景模型几何之间的边缘是否存在碰撞，以及从图形中移除任何 边缘有碰撞。 如果路径边缘没有碰撞，则将路径指定为成功路径，并通过数据处理系统向用户显示成功的路径。

公开(公告)号：WO2008150889A1

公开(公告)日：2008-12-11

申请号：PCT/US2008/065120

申请日：2008-05-29

申请人： MAGMA DESIGN AUTOMATION, INC. ,  BANERJEE, Joy ,  JIANG, Yunjian ,  SRINIVASAN, Arvind ,  LI, Yinghua ,  DAS, Partha ,  CHAUDHURI, Samit

发明人： BANERJEE, Joy ,  JIANG, Yunjian ,  SRINIVASAN, Arvind ,  LI, Yinghua ,  DAS, Partha ,  CHAUDHURI, Samit

IPC分类号： H03K19/00

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/08

摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

摘要翻译： 提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。 合成网表中的块被标识为空闲候选块。 芯片上的子块被聚集成一个集群。 对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。 根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。

公开(公告)号：WO2008044211A1

公开(公告)日：2008-04-17

申请号：PCT/IB2007/054122

申请日：2007-10-10

申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) ,  MURALI, Srinivasan ,  LUCA, Benini ,  DE MICHELI, Giovanni

发明人： MURALI, Srinivasan ,  LUCA, Benini ,  DE MICHELI, Giovanni

IPC分类号： G06F17/50 ,  G06F13/00 ,  H04L12/56

CPC分类号： G06F17/5045 ,  G06F2217/08 ,  H04L49/25

摘要： To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific architecture that satisfies the objectives and constraints of the targeted application domain is required. In this work we present a method for synthesizing such application-specific NoC architectures. This best topology is achieved by a method to design Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements such as processors, hardware blocks, memories, communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of: - obtaining predefined communication characteristics modelling the applications running on the multicore system, - establishing the number and configuration of switches to connect the elements, - establishing physical connectivity between the elements and the switches, - for each of at least two pairs of communicating elements : a defining a communication path, that is, a sequence of switches to be traversed to connect the aforementioned pair of communicating elements, b calculating metrics as affected by the need to render said path into physical connectivity, said metrics being selected among one or a combination of power consumption of the involved switches, area of the involved switches, number of inputs and outputs of the involved switches, total length of wires used, maximum possible speed of operation of the system and number of switches to be traversed, taking into account any previously defined physical connectivity, c iterating the steps a and b for a plurality of possible paths, d choosing the path having the optimal metrics, e establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connected switches.

摘要翻译： 为了解决多核系统日益增长的通信复杂性，需要可扩展的芯片上的网络（NoC）来互连系统的处理器，内存和硬件核心。 为了在今天的工业设计中使用NoCc可行，需要一种满足目标应用领域目标和约束条件的定制的，特定于应用的架构。 在这项工作中，我们提出了一种合成这种特定于应用程序的NoC架构的方法。 该最佳拓扑通过一种设计基于芯片上的网络（NoC）的通信系统来实现，该通信系统用于连接多核系统中的片上组件，所述系统包括若干元件，例如处理器，硬件块，存储器，通过通信系统进行通信 所述通信系统至少包括交换机，所述方法包括以下步骤： - 获得对在多核系统上运行的应用建模的预定义的通信特性， - 建立用于连接元件的交换机的数量和配置， - 建立元件之间的物理连接 和交换机，用于至少两对通信元件中的每一个：定义通信路径，即要穿过的交换机序列以连接前述的一对通信元件，b计算受需要影响的度量 将所述路径呈现为物理连接，所述度量在一个或一个中选择 所涉及的交换机的功耗组合，所涉及的交换机的面积，所涉及的交换机的输入和输出的数量，使用的电线的总长度，系统的最大可能的运行速度和要经过的开关的数量，考虑到 任何先前定义的物理连接，c迭代多个可能路径的步骤a和b，d选择具有最佳度量的路径，e在交换机之间建立任何缺少的物理连接，使得所选择的最佳路径跨物理连接的交换机发生。

公开(公告)号：WO2005111797A3

公开(公告)日：2007-12-06

申请号：PCT/US2005016263

申请日：2005-05-09

申请人： UNIV MICHIGAN STATE ,  AVERILL RONALD C ,  SIDHU RAN MOHAN JIT SINGH ,  HALEPATALI PRAVEEN

发明人： AVERILL RONALD C ,  SIDHU RAN MOHAN JIT SINGH ,  HALEPATALI PRAVEEN

IPC分类号： G06F17/50 ,  G05B19/42 ,  G06F7/60 ,  G06F9/44 ,  G06F9/455 ,  G06F15/18 ,  G06F17/10 ,  G06F19/00 ,  G06N3/00 ,  G06N3/12

CPC分类号： G06F8/20 ,  G06F17/50 ,  G06F2217/08 ,  G06F2217/10 ,  G06Q10/04 ,  Y02T10/82

摘要： A design optimization system includes an initial design evaluation module evaluating a system model using initial subsystem designs to extract interactions between subsystem models and/or between the system (60) and the subsystem models (70, 80, 90, 100, 110, 120, 130, 140). An updating module updates the interactions for the subsystem models, and an optimization module performs subsystem design optimization using the subsystem model and most recently updated interactions, thereby obtaining an updated subsystem design.

摘要翻译： 设计优化系统包括初始设计评估模块，其使用初始子系统设计来评估系统模型，以提取子系统模型之间和/或系统（60）和子系统模型 130，140）。 更新模块更新子系统模型的交互，优化模块使用子系统模型和最近更新的交互来执行子系统设计优化，从而获得更新的子系统设计。

公开(公告)号：WO2007016106A2

公开(公告)日：2007-02-08

申请号：PCT/US2006/028873

申请日：2006-07-25

申请人： CAN TECHNOLOGIES, INC. ,  CARGILL, INCORPORATED ,  PASZEK, Adam, Albert ,  BURGHARDI, Steve, R. ,  COOK, David, A. ,  ENGELKE, Gregory, L. ,  GIESTING, Donald, W. ,  KNUDSON, Brian ,  MCGOOGAN, Bruce, Brim ,  MESSMAN, Michael ,  NEWCOMB, Mark, D. ,  VAN DE LIGT, Jennifer, L., G.

发明人： PASZEK, Adam, Albert ,  BURGHARDI, Steve, R. ,  COOK, David, A. ,  ENGELKE, Gregory, L. ,  GIESTING, Donald, W. ,  KNUDSON, Brian ,  MCGOOGAN, Bruce, Brim ,  MESSMAN, Michael ,  NEWCOMB, Mark, D. ,  VAN DE LIGT, Jennifer, L., G.

IPC分类号： G06Q10/00

CPC分类号： G06Q50/02 ,  G06F17/5009 ,  G06F2217/08 ,  G06Q10/04

摘要： A system for generating optimized values for variable inputs to an animal production system. The system includes a simulator engine configured to receive a plurality of animal information inputs and generate a performance projection. At least one of the animal information inputs is designated as a variable input and at least one of the animal information inputs includes animal genotype information. The system further includes an enterprise supervisor engine configured to generate an optimized value for at least one variable input wherein the optimized value is configured to optimize animal production based on the animal genotype information.

摘要翻译： 用于为动物生产系统的可变输入生成优化值的系统。 该系统包括被配置为接收多个动物信息输入并产生性能投影的模拟器引擎。 动物信息输入中的至少一个被指定为可变输入，并且动物信息输入中的至少一个包括动物基因型信息。 该系统还包括配置成为至少一个可变输入生成优化值的企业管理引擎，其中优化值被配置为基于动物基因型信息优化动物生产。

公开(公告)号：WO2006069934A3

公开(公告)日：2007-01-04

申请号：PCT/EP2005056953

申请日：2005-12-20

申请人： SIEMENS AG ,  SUTOR ARIANE

发明人： SUTOR ARIANE

IPC分类号： G06F17/50 ,  G06F17/10 ,  G06Q10/00

CPC分类号： G06Q10/04 ,  G06F17/11 ,  G06F17/50 ,  G06F2217/08

摘要： The invention relates to the use of a method for designing a technical system, said technical system comprising a target function (f(i, x)) that depends on at least one continuous variable (x) and at least one discreet variable (i). The at least one continuous variable (x) supposes a plurality of continuous parameters (xij) and the at least one discreet variable (i) can suppose a plurality of discreet parameters (ij). A first optimisation method and a second optimisation method are carried out according to the inventive method, and the target functional value ((f(ij+1,xij+1)) determined by the inventive method, in addition to the associated discreet and continuous parameters (ij+1, xij+1)), are used to design the technical system. The inventive method optimises the technical system in a simple and efficient manner both in terms of discreet and continuous parameters. Said method is used by a processor unit to solve a high-dimensional target function (f(i, x)).

摘要翻译： 本发明涉及一种使用的方法的用于设计技术系统，其中所述技术系统包括目标函数（f（I，X））从至少一个连续变量衍生的（x）和至少一个离散变量（i）是相关的，其特征在于 （xij），并且所述至少一个离散的变量（i）的多个离散的参数（IJ）的可以接受至少一个连续变量（x）的多个连续参数。 在该方法中，第一优化过程和一第二优化处理被执行，从而确定的目标函数值（（F（I，J + 1，X IJ + 1））和（其离散和连续参数IJ + 1，X IJ + 1））是对草案 技术系统设置一次。 过程优化简单和有效的既在离散的和连续参数方面的技术系统。 该方法用于高维目标函数的溶液中使用由处理器单元（F（I，X））。